Merge remote-tracking branch 'upstream/master'

Change-Id: I754ba57320720ff7f46e34d80b1719a37dcd3d1e

README.md

@@ -18,6 +18,8 @@ address. This allows direct connection to (Xilinx) block RAMs. When
 using asynchronous memory, I suggest registering the address/control
 lines for glitchless output signals.
 
+[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02)
+
 Have fun. 
 
 ==========

cpu.v

@@ -836,15 +836,6 @@ always @(posedge clk )
  * time to read the IR again before the next decode.
  */
 
-reg RDY1 = 1;
-
-always @(posedge clk )
-    RDY1 <= RDY;
-
-always @(posedge clk )
-    if( ~RDY && RDY1 )
-        DIHOLD <= DI;
-
 always @(posedge clk )
     if( reset )
         IRHOLD_valid <= 0;
@@ -859,7 +850,11 @@ always @(posedge clk )
 assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
                      IRHOLD_valid ? IRHOLD : DIMUX;
 
-assign DIMUX = ~RDY1 ? DIHOLD : DI;
+always @(posedge clk )
+    if( RDY )
+        DIHOLD <= DI;
+
+assign DIMUX = ~RDY ? DIHOLD : DI;
 
 /*
  * Microcode state machine