third-party/verilog-6502
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Added fix for 1-cycle RDY bug

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This commit is contained in:
Arlet Ottens
2016-08-19 20:19:40 +02:00
parent ae653ab688
commit a11631082b
1 changed files with 5 additions and 10 deletions
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15
cpu.v
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@@ -836,15 +836,6 @@ always @(posedge clk )
* time to read the IR again before the next decode. * time to read the IR again before the next decode.
*/ */
reg RDY1 = 1;
always @(posedge clk )
RDY1 <= RDY;
always @(posedge clk )
if( ~RDY && RDY1 )
DIHOLD <= DI;
always @(posedge clk ) always @(posedge clk )
if( reset ) if( reset )
IRHOLD_valid <= 0; IRHOLD_valid <= 0;
@@ -859,7 +850,11 @@ always @(posedge clk )
assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 : assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 :
IRHOLD_valid ? IRHOLD : DIMUX; IRHOLD_valid ? IRHOLD : DIMUX;
assign DIMUX = ~RDY1 ? DIHOLD : DI; always @(posedge clk )
if( RDY )
DIHOLD <= DI;
assign DIMUX = ~RDY ? DIHOLD : DI;
/* /*
* Microcode state machine * Microcode state machine