fix for bit/logic verilator keywords

ALU.v

@@ -42,7 +42,7 @@ reg HC;
 
 reg AI7;
 reg BI7;
-reg [8:0] logic;
+reg [8:0] temp_logic;
 reg [7:0] temp_BI;
 reg [4:0] temp_l;
 reg [4:0] temp_h;
@@ -54,14 +54,14 @@ wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
 // F5MUX.
 always @*  begin
 	case( op[1:0] )
-	    2'b00: logic = AI | BI;
-	    2'b01: logic = AI & BI;
-	    2'b10: logic = AI ^ BI;
-	    2'b11: logic = AI;
+	    2'b00: temp_logic = AI | BI;
+	    2'b01: temp_logic = AI & BI;
+	    2'b10: temp_logic = AI ^ BI;
+	    2'b11: temp_logic = AI;
 	endcase
 
 	if( right )
-	    logic = { AI[0], CI, AI[7:1] };
+	    temp_logic = { AI[0], CI, AI[7:1] };
 end
 
 // Add logic result to BI input. This only makes sense when logic = AI.
@@ -70,7 +70,7 @@ always @* begin
 	case( op[3:2] )
 	    2'b00: temp_BI = BI;	// A+B
 	    2'b01: temp_BI = ~BI;	// A-B
-	    2'b10: temp_BI = logic;	// A+A
+	    2'b10: temp_BI = temp_logic;	// A+A
 	    2'b11: temp_BI = 0;		// A+0
 	endcase	
 end
@@ -87,8 +87,8 @@ wire temp_HC = temp_l[4] | HC9;
 // perform the addition as 2 separate nibble, so we get
 // access to the half carry flag
 always @* begin
-	temp_l = logic[3:0] + temp_BI[3:0] + adder_CI;
-	temp_h = logic[8:4] + temp_BI[7:4] + temp_HC;
+	temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
+	temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
 end
 
 // calculate the flags