third-party/verilog-6502
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fix for bit/logic verilator keywords

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This commit is contained in:
Arlet Ottens
2014-10-23 20:33:44 +02:00
parent 74e83fa07f
commit dff3abaaac
2 changed files with 644 additions and 644 deletions
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18
ALU.v
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@@ -42,7 +42,7 @@ reg HC;
reg AI7;
reg BI7;
reg [8:0] logic;
reg [8:0] temp_logic;
reg [7:0] temp_BI;
reg [4:0] temp_l;
reg [4:0] temp_h;
@@ -54,14 +54,14 @@ wire adder_CI = (right | (op[3:2] == 2'b11)) ? 0 : CI;
// F5MUX.
always @* begin
case( op[1:0] )
2'b00: logic = AI | BI;
2'b01: logic = AI & BI;
2'b10: logic = AI ^ BI;
2'b11: logic = AI;
2'b00: temp_logic = AI | BI;
2'b01: temp_logic = AI & BI;
2'b10: temp_logic = AI ^ BI;
2'b11: temp_logic = AI;
endcase
if( right )
logic = { AI[0], CI, AI[7:1] };
temp_logic = { AI[0], CI, AI[7:1] };
end
// Add logic result to BI input. This only makes sense when logic = AI.
@@ -70,7 +70,7 @@ always @* begin
case( op[3:2] )
2'b00: temp_BI = BI; // A+B
2'b01: temp_BI = ~BI; // A-B
2'b10: temp_BI = logic; // A+A
2'b10: temp_BI = temp_logic; // A+A
2'b11: temp_BI = 0; // A+0
endcase
end
@@ -87,8 +87,8 @@ wire temp_HC = temp_l[4] | HC9;
// perform the addition as 2 separate nibble, so we get
// access to the half carry flag
always @* begin
temp_l = logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = logic[8:4] + temp_BI[7:4] + temp_HC;
temp_l = temp_logic[3:0] + temp_BI[3:0] + adder_CI;
temp_h = temp_logic[8:4] + temp_BI[7:4] + temp_HC;
end
// calculate the flags

12
cpu.v
View File

@@ -135,7 +135,7 @@ reg adj_bcd; // results should be BCD adjusted
* some flip flops to remember we're doing special instructions. These
* get loaded at the DECODE state, and used later
*/
reg bit; // doing BIT instruction
reg bit_ins; // doing BIT instruction
reg plp; // doing PLP instruction
reg php; // doing PHP instruction
reg clc; // clear carry
@@ -769,7 +769,7 @@ always @(posedge clk)
else if( state == DECODE ) begin
if( plp )
Z <= ADD[1];
else if( (load_reg & (regsel != SEL_S)) | compare | bit )
else if( (load_reg & (regsel != SEL_S)) | compare | bit_ins )
Z <= AZ;
end
@@ -783,7 +783,7 @@ always @(posedge clk)
N <= ADD[7];
else if( (load_reg & (regsel != SEL_S)) | compare )
N <= AN;
end else if( state == FETCH && bit )
end else if( state == FETCH && bit_ins )
N <= DIMUX[7];
/*
@@ -823,7 +823,7 @@ always @(posedge clk )
if( adc_sbc ) V <= AV;
if( clv ) V <= 0;
if( plp ) V <= ADD[6];
end else if( state == FETCH && bit )
end else if( state == FETCH && bit_ins )
V <= DIMUX[6];
/*
@@ -1172,9 +1172,9 @@ always @(posedge clk )
if( state == DECODE && RDY )
casex( IR )
8'b0010_x100: // BIT zp/abs
bit <= 1;
bit_ins <= 1;
default: bit <= 0;
default: bit_ins <= 0;
endcase
/*