third-party/verilog-6502
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c51aa17b6b1a4de23184815fd404b4670186f8ae
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Arlet c51aa17b6b Fixed '=' back to '<=' for 'backwards' signal.
2011-06-08 06:54:11 +02:00
ALU.v
Added support for RDY
2011-05-16 14:31:22 +02:00
cpu.v
Fixed '=' back to '<=' for 'backwards' signal.
2011-06-08 06:54:11 +02:00
README
first commit
2011-05-02 19:04:14 +02:00

README 

A Verilog HDL version of the old MOS 6502 CPU.

Have fun.
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Readme 81 KiB
Languages
Verilog 100%