11 lines
434 B
Markdown
11 lines
434 B
Markdown
A Verilog HDL version of the old MOS 6502 CPU.
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Note: the 6502 core assumes a synchronous memory. This means that valid
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data (DI) is expected on the cycle *after* valid address. This allows
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direct connection to (Xilinx) block RAMs. When using asynchronous memory,
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I suggest registering the address/control lines for glitchless output signals.
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[Also check out my new 65C02 project](https://github.com/Arlet/verilog-65c02)
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Have fun.
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