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Created with Raphaël 2.2.010Mar26Feb25236Aug12Apr28Jan261716Aug1427Jul2617Feb1329Jan2529Dec81Nov18Sep715May1330Mar27Dec1029Nov28252415220Oct171328Sep127Aug25173Jun231May302518163Apr3Dec7Sep6317Aug10Jul17Apr27Mar19Feb1824Oct9Aug25Jul24181610Jun926Apr28Mar2726727Feb9Dec8328Nov30Oct25249Sep15Aug92Jul30Jun1327Feb2621Nov201218May12Sep224Aug232221427Jul25242027Jun5Jan9Nov8719Oct9814Jul13922Jun512May8319Apr21Mar28Feb3Dec21Nov1916131298528Oct22212030Sep1913Add missing length parametermastermasterAdd commaAdd another waiverAdd non-opt flagAdd verilator.vltPull changes from verilog-ethernetAdd sources.listParameter fix for ISEAdd support for file list filesFix tkeep handling in axis_adapterForce AXIS RAM switch output FIFO into distributed RAMFix spurious multi-driven net issue in axis_ram_switch when S_ID_WIDTH = 0Remove stall cycle in axis_arb_muxFix FIFO output pause logicImplement MARK_WHEN_FULL option in FIFOsReorganize FIFO write logicTest DROP_WHEN_FULL parameterAdd overflow test, previous test is actually an oversize frame testSend more data in stress testsCompute DEPTH based on FIFO data widthUse FIFO depth in overflow testRead configuration directly from DUTAdd pause functionality to FIFO modulesRewrite width converter to reduce resource consumptionReorganize FIFO adapter wrappersReorganize pipeline FIFO to facilitate placement constraintsAdd depth status outputs to FIFOsRefactor pointer handling in FIFOsRemove extraneous parametersAnother update to async FIFO timing constraints to deal with OOC clock constraintsRemove recursively-expanded macros for module parameters in makefilesUpdate ubuntu version in CIRework parameter handling in testbench makefilesUpdate CI configurationRemove separate memory read register (it causes ISE to crash, and is not necessary for URAM inference)Update async FIFO timing constraints to handle clocks from OOC IP that are not constrained during synthesisUpdate async FIFO timing constraintsAdd option for output FIFO to improve pipelining and RAM inference for large FIFOsConsolidated RAM pipeline output wiresUse separate RAM output register for better pipeline register inference