Initial Commit - Forked from PeakRDL-regblock @ a440cc19769069be831d267505da4f3789a26695

hdl-src/README.md

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+# HDL Source Files
+This folder contains some SystemVerilog definitions that are useful collateral
+to be used alongside this project.
+
+These reference files are free to use for any purpose and are not covered by
+this project's LGPLv3 license.
+
+If for whatever reason you feel the need to reference a license when using
+these, then lets go with the [MIT License](https://choosealicense.com/licenses/mit/)

hdl-src/apb3_intf.sv

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+interface apb3_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    // Command
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+
+    // Response
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    modport master (
+        output PSEL,
+        output PENABLE,
+        output PWRITE,
+        output PADDR,
+        output PWDATA,
+
+        input PRDATA,
+        input PREADY,
+        input PSLVERR
+    );
+
+    modport slave (
+        input PSEL,
+        input PENABLE,
+        input PWRITE,
+        input PADDR,
+        input PWDATA,
+
+        output PRDATA,
+        output PREADY,
+        output PSLVERR
+    );
+endinterface

hdl-src/apb4_intf.sv

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+interface apb4_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    // Command
+    logic PSEL;
+    logic PENABLE;
+    logic PWRITE;
+    logic [2:0] PPROT;
+    logic [ADDR_WIDTH-1:0] PADDR;
+    logic [DATA_WIDTH-1:0] PWDATA;
+    logic [DATA_WIDTH/8-1:0] PSTRB;
+
+    // Response
+    logic [DATA_WIDTH-1:0] PRDATA;
+    logic PREADY;
+    logic PSLVERR;
+
+    modport master (
+        output PSEL,
+        output PENABLE,
+        output PWRITE,
+        output PPROT,
+        output PADDR,
+        output PWDATA,
+        output PSTRB,
+
+        input PRDATA,
+        input PREADY,
+        input PSLVERR
+    );
+
+    modport slave (
+        input PSEL,
+        input PENABLE,
+        input PWRITE,
+        input PPROT,
+        input PADDR,
+        input PWDATA,
+        input PSTRB,
+
+        output PRDATA,
+        output PREADY,
+        output PSLVERR
+    );
+endinterface

hdl-src/avalon_mm_intf.sv

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+interface avalon_mm_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32 // Important! Avalon uses word addressing
+);
+    // Command
+    logic read;
+    logic write;
+    logic waitrequest;
+    logic [ADDR_WIDTH-1:0] address;
+    logic [DATA_WIDTH-1:0] writedata;
+    logic [DATA_WIDTH/8-1:0] byteenable;
+
+    // Response
+    logic readdatavalid;
+    logic writeresponsevalid;
+    logic [DATA_WIDTH-1:0] readdata;
+    logic [1:0] response;
+
+    modport host (
+        output read,
+        output write,
+        input waitrequest,
+        output address,
+        output writedata,
+        output byteenable,
+
+        input readdatavalid,
+        input writeresponsevalid,
+        input readdata,
+        input response
+    );
+
+    modport agent (
+        input read,
+        input write,
+        output waitrequest,
+        input address,
+        input writedata,
+        input byteenable,
+
+        output readdatavalid,
+        output writeresponsevalid,
+        output readdata,
+        output response
+    );
+endinterface

hdl-src/axi4lite_intf.sv

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+interface axi4lite_intf #(
+    parameter DATA_WIDTH = 32,
+    parameter ADDR_WIDTH = 32
+);
+    logic AWREADY;
+    logic AWVALID;
+    logic [ADDR_WIDTH-1:0] AWADDR;
+    logic [2:0] AWPROT;
+
+    logic WREADY;
+    logic WVALID;
+    logic [DATA_WIDTH-1:0] WDATA;
+    logic [DATA_WIDTH/8-1:0] WSTRB;
+
+    logic BREADY;
+    logic BVALID;
+    logic [1:0] BRESP;
+
+    logic ARREADY;
+    logic ARVALID;
+    logic [ADDR_WIDTH-1:0] ARADDR;
+    logic [2:0] ARPROT;
+
+    logic RREADY;
+    logic RVALID;
+    logic [DATA_WIDTH-1:0] RDATA;
+    logic [1:0] RRESP;
+
+    modport master (
+        input AWREADY,
+        output AWVALID,
+        output AWADDR,
+        output AWPROT,
+
+        input WREADY,
+        output WVALID,
+        output WDATA,
+        output WSTRB,
+
+        output BREADY,
+        input BVALID,
+        input BRESP,
+
+        input ARREADY,
+        output ARVALID,
+        output ARADDR,
+        output ARPROT,
+
+        output RREADY,
+        input RVALID,
+        input RDATA,
+        input RRESP
+    );
+
+    modport slave (
+        output AWREADY,
+        input AWVALID,
+        input AWADDR,
+        input AWPROT,
+
+        output WREADY,
+        input WVALID,
+        input WDATA,
+        input WSTRB,
+
+        input BREADY,
+        output BVALID,
+        output BRESP,
+
+        output ARREADY,
+        input ARVALID,
+        input ARADDR,
+        input ARPROT,
+
+        input RREADY,
+        output RVALID,
+        output RDATA,
+        output RRESP
+    );
+endinterface

hdl-src/regblock_udps.rdl

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+/*
+ * This file defines several property extensions that are understood by the
+ * PeakRDL-Regblock SystemVerilog code generator.
+ *
+ * Compile this file prior to your other SystemRDL sources.
+ *
+ * For more details, see: https://peakrdl-regblock.readthedocs.io/en/latest/udps/intro.html
+ */
+
+property buffer_reads {
+    component = reg;
+    type = boolean;
+};
+
+property rbuffer_trigger {
+    component = reg;
+    type = ref;
+};
+
+property buffer_writes {
+    component = reg;
+    type = boolean;
+};
+
+property wbuffer_trigger {
+    component = reg;
+    type = ref;
+};
+
+property rd_swacc {
+    component = field;
+    type = boolean;
+};
+
+property wr_swacc {
+    component = field;
+    type = boolean;
+};
+
+property is_signed {
+    type = boolean;
+    component = field;
+    default = true;
+};
+
+property intwidth {
+    type = longint unsigned;
+    component = field;
+};
+
+property fracwidth {
+    type = longint unsigned;
+    component = field;
+};