04971bdb8e
* Initial plan * Fix non-synthesizable code for nested addrmaps with arrays Fixed bug where array dimensions were used instead of strides in decode logic. For nested addrmaps with arrays like inner[4] @ 0x0 += 0x100, the generated code was incorrectly using the dimension (4) instead of the stride (0x100). This resulted in non-synthesizable SystemVerilog with incorrect address decoding. The fix calculates proper strides for each dimension, including support for multi-dimensional arrays like [2][3] where each dimension has a different stride. Added comprehensive tests to prevent regression. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> * Improve code comments for stride calculation clarity Added more detailed comments explaining the stride calculation logic, including a concrete example showing how strides are calculated for multi-dimensional arrays. Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
Tests
The bus decoder exporter includes comprehensive test suites to validate both the Python implementation and the generated SystemVerilog RTL.
Unit Tests
The unit test suite is built around pytest and exercises the Python implementation
directly using the systemrdl-compiler
package to elaborate inline SystemRDL snippets.
Install dependencies
Create an isolated environment if desired and install the minimal requirements:
# Using uv (recommended)
uv sync --group test
# Or using pip
python -m pip install -e . parameterized pytest pytest-cov pytest-xdist
Running the suite
Invoke pytest from the repository root (or the tests directory) and point it
at the unit tests:
pytest tests/unit
Pytest will automatically discover tests that follow the test_*.py naming
pattern and can make use of the compile_rdl fixture defined in
tests/unit/conftest.py to compile inline SystemRDL sources.
Cocotb Integration Tests
The cocotb test suite validates the functionality of generated SystemVerilog RTL through simulation. These tests generate bus decoders for different CPU interfaces (APB3, APB4, AXI4-Lite) and verify that read/write operations work correctly.
Install dependencies
# Install with cocotb support using uv (recommended)
uv sync --group test
# Or using pip
python -m pip install -e . parameterized pytest pytest-cov pytest-xdist cocotb cocotb-bus
# Install HDL simulator (choose one)
apt-get install iverilog # Icarus Verilog
apt-get install verilator # Verilator
Running the tests
Integration tests (no simulator required)
These tests validate code generation without requiring an HDL simulator:
pytest tests/cocotb/testbenches/test_integration.py -v
Example code generation
Run examples to see generated code for different configurations:
python tests/cocotb/examples.py
Full simulation tests (requires simulator)
To run the full cocotb simulation tests:
# Run all cocotb simulation tests
pytest tests/cocotb/testbenches/test_*_runner.py -v
# Run specific interface tests
pytest tests/cocotb/testbenches/test_apb4_runner.py -v
For more information about cocotb tests, see tests/cocotb/README.md.