70 lines
1.8 KiB
TOML
70 lines
1.8 KiB
TOML
[build-system]
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requires = ["setuptools", "setuptools-scm"]
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build-backend = "setuptools.build_meta"
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[project]
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name = "peakrdl-busdecoder"
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version = "0.1.0"
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requires-python = ">=3.10"
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dependencies = [
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"jinja2>=3.1.6",
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"systemrdl-compiler~=1.30.1",
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]
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authors = [{ name = "Alex Mykyta" }]
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description = "Compile SystemRDL into a SystemVerilog control/status register (CSR) block"
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readme = "README.md"
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license = { text = "LGPLv3" }
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keywords = [
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"SystemRDL",
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"PeakRDL",
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"CSR",
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"compiler",
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"tool",
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"registers",
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"generator",
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"Verilog",
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"SystemVerilog",
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"register abstraction layer",
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"FPGA",
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"ASIC",
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]
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classifiers = [
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"Development Status :: 5 - Production/Stable",
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"Programming Language :: Python",
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"Programming Language :: Python :: 3",
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"Programming Language :: Python :: 3 :: Only",
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"Intended Audience :: Developers",
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"License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)",
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"Operating System :: OS Independent",
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"Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)",
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]
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[project.optional-dependencies]
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cli = ["peakrdl-cli >= 1.2.3"]
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[project.urls]
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Source = "https://github.com/SystemRDL/PeakRDL-busdecoder"
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Tracker = "https://github.com/SystemRDL/PeakRDL-busdecoder/issues"
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Changelog = "https://github.com/SystemRDL/PeakRDL-busdecoder/releases"
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Documentation = "https://peakrdl-busdecoder.readthedocs.io/"
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[dependency-groups]
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docs = [
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"pygments-systemrdl>=1.3.0",
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"sphinx-book-theme>=1.1.4",
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"sphinxcontrib-wavedrom>=3.0.4",
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]
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test = [
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"parameterized>=0.9.0",
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"pytest>=7.4.4",
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"pytest-cov>=4.1.0",
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"pytest-xdist>=3.5.0",
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]
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tools = [
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"ruff>=0.14.0",
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]
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[project.entry-points."peakrdl.exporters"]
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busdecoder = "peakrdl_busdecoder.__peakrdl__:Exporter"
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