516da7a43bc90498276b61012285e755258040cb
* Initial plan * Fix APB3 and APB4 flat bus decoder implementations by adding missing fanout, fanin, and readback methods Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com> --------- Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com> Co-authored-by: arnavsacheti <36746504+arnavsacheti@users.noreply.github.com>
PeakRDL-busdecoder
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
Documentation
See the PeakRDL-busdecoder Documentation for more details
Description
Languages
Python
93.6%
SystemVerilog
6.2%
Dockerfile
0.2%