bslathi19/PeakRDL-regblock
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Discard LSbs of address for AXI4-Lite CPUIF to properly handle unaligned transfers. #60

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This commit is contained in:
Alex Mykyta
2023-08-24 20:36:28 -07:00
parent eef8f7cdb4
commit 280c3aad17
3 changed files with 14 additions and 2 deletions
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2
src/peakrdl_regblock/cpuif/apb3/apb3_tmpl.sv
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@@ -13,7 +13,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
is_active <= '1;
cpuif_req <= '1;
cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
{%- if cpuif.data_width == 8 %}
{%- if cpuif.data_width_bytes == 1 %}
cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
{%- else %}
cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};

2
src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
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@@ -14,7 +14,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
is_active <= '1;
cpuif_req <= '1;
cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
{%- if cpuif.data_width == 8 %}
{%- if cpuif.data_width_bytes == 1 %}
cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
{%- else %}
cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};

12
src/peakrdl_regblock/cpuif/axi4lite/axi4lite_tmpl.sv
View File

@@ -83,17 +83,29 @@ always_comb begin
if(axil_arvalid && !axil_prev_was_rd) begin
cpuif_req = '1;
cpuif_req_is_wr = '0;
{%- if cpuif.data_width_bytes == 1 %}
cpuif_addr = axil_araddr;
{%- else %}
cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
{%- endif %}
if(!cpuif_req_stall_rd) axil_ar_accept = '1;
end else if(axil_awvalid && axil_wvalid) begin
cpuif_req = '1;
cpuif_req_is_wr = '1;
{%- if cpuif.data_width_bytes == 1 %}
cpuif_addr = axil_awaddr;
{%- else %}
cpuif_addr = {axil_awaddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
{%- endif %}
if(!cpuif_req_stall_wr) axil_aw_accept = '1;
end else if(axil_arvalid) begin
cpuif_req = '1;
cpuif_req_is_wr = '0;
{%- if cpuif.data_width_bytes == 1 %}
cpuif_addr = axil_araddr;
{%- else %}
cpuif_addr = {axil_araddr[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};
{%- endif %}
if(!cpuif_req_stall_rd) axil_ar_accept = '1;
end
end