Discard LSbs of address for AXI4-Lite CPUIF to properly handle unaligned transfers. #60

2023-08-24 20:36:28 -07:00
parent eef8f7cdb4
commit 280c3aad17
3 changed files with 14 additions and 2 deletions
--- a/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
+++ b/src/peakrdl_regblock/cpuif/apb4/apb4_tmpl.sv
@@ -14,7 +14,7 @@ always_ff {{get_always_ff_event(cpuif.reset)}} begin
                is_active <= '1;
                cpuif_req <= '1;
                cpuif_req_is_wr <= {{cpuif.signal("pwrite")}};
-                {%- if cpuif.data_width == 8 %}
+                {%- if cpuif.data_width_bytes == 1 %}
                cpuif_addr <= {{cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:0];
                {%- else %}
                cpuif_addr <= { {{-cpuif.signal("paddr")}}[{{cpuif.addr_width-1}}:{{clog2(cpuif.data_width_bytes)}}], {{clog2(cpuif.data_width_bytes)}}'b0};