Doc fixes. Add banner to output

2022-03-16 20:53:55 -07:00
parent b9570480be
commit 746f6cb020
7 changed files with 12 additions and 9 deletions
--- a/src/peakrdl/regblock/field_logic/init.py
+++ b/src/peakrdl/regblock/field_logic/init.py
@@ -266,7 +266,6 @@ class FieldLogic:
        same assignment precedence.
        """

-        # TODO: Add all the other things
        self.add_sw_conditional(sw_onread.ClearOnRead(self.exp), AssignmentPrecedence.SW_ONREAD)
        self.add_sw_conditional(sw_onread.SetOnRead(self.exp), AssignmentPrecedence.SW_ONREAD)

--- a/src/peakrdl/regblock/module_tmpl.sv
+++ b/src/peakrdl/regblock/module_tmpl.sv
@@ -1,4 +1,6 @@
-// TODO: Add a banner
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
 module {{module_name}} (
        input wire clk,
        input wire rst,
--- a/src/peakrdl/regblock/package_tmpl.sv
+++ b/src/peakrdl/regblock/package_tmpl.sv
@@ -1,4 +1,6 @@
-// TODO: Add a banner
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
 package {{hwif.package_name}};
    {{hwif.get_package_contents()|indent}}
 endpackage