Doc fixes. Add banner to output

docs/architecture.rst

@@ -3,7 +3,7 @@ Register Block Architecture
 
 The generated register block RTL is organized into several sections.
 Each section is automatically generated based on the source register model and
-is rendered into the output register block SystermVerilog RTL.
+is rendered into the output register block SystemVerilog RTL.
 
 .. figure:: diagrams/arch.png
 

docs/cpuif/apb3.rst

@@ -10,10 +10,10 @@ The APB3 CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif`
 
-    Interface Definition: :download:`apb3_intf.sv <../../test/lib/cpuifs/apb3/apb3_intf.sv>`
+    Interface Definition: :download:`apb3_intf.sv <../../tests/lib/cpuifs/apb3/apb3_intf.sv>`
 
 Flattened inputs/outputs
-    Flattens the interface into descrete input and output ports.
+    Flattens the interface into discrete input and output ports.
 
     Class: :class:`peakrdl.regblock.cpuif.apb3.APB3_Cpuif_flattened`
 

docs/cpuif/axi4lite.rst

@@ -12,10 +12,10 @@ The AXI4-Lite CPU interface comes in two i/o port flavors:
 SystemVerilog Interface
     Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif`
 
-    Interface Definition: :download:`apb3_intf.sv <../../test/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
+    Interface Definition: :download:`axi4lite_intf.sv <../../tests/lib/cpuifs/axi4lite/axi4lite_intf.sv>`
 
 Flattened inputs/outputs
-    Flattens the interface into descrete input and output ports.
+    Flattens the interface into discrete input and output ports.
 
     Class: :class:`peakrdl.regblock.cpuif.axi4lite.AXI4Lite_Cpuif_flattened`
 

docs/hwif.rst

@@ -8,7 +8,7 @@ using two struct ports:
 * ``hwif_out``
 
 All field inputs and outputs as well as signals are consolidated into these
-struct ports. The presence of each depends on the specific contents of the desgin
+struct ports. The presence of each depends on the specific contents of the design
 being exported.
 
 

src/peakrdl/regblock/field_logic/__init__.py

@@ -266,7 +266,6 @@ class FieldLogic:
         same assignment precedence.
         """
 
-        # TODO: Add all the other things
         self.add_sw_conditional(sw_onread.ClearOnRead(self.exp), AssignmentPrecedence.SW_ONREAD)
         self.add_sw_conditional(sw_onread.SetOnRead(self.exp), AssignmentPrecedence.SW_ONREAD)
 

src/peakrdl/regblock/module_tmpl.sv

@@ -1,4 +1,6 @@
-// TODO: Add a banner
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
 module {{module_name}} (
         input wire clk,
         input wire rst,

src/peakrdl/regblock/package_tmpl.sv

@@ -1,4 +1,6 @@
-// TODO: Add a banner
+// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
+//  https://github.com/SystemRDL/PeakRDL-regblock
+
 package {{hwif.package_name}};
     {{hwif.get_package_contents()|indent}}
 endpackage