Add pre-production warning

2022-07-29 23:32:15 -07:00
parent 860e5fecf9
commit 8b82f9f725
1 changed files with 4 additions and 0 deletions
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -12,6 +12,10 @@ your hardware design.
 * Broad support for SystemRDL 2.0 features
 * Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus

+.. warning::
+
+    The PeakRDL-regblock SV generator is still in pre-production (v0.x version numbers).
+    During this time, I may decide to refactor things which could break compatibility.


 Installing