bslathi19/PeakRDL-regblock
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Add pre-production warning

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Alex Mykyta
2022-07-29 23:32:15 -07:00
parent 860e5fecf9
commit 8b82f9f725
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docs/index.rst
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@@ -12,6 +12,10 @@ your hardware design.
* Broad support for SystemRDL 2.0 features * Broad support for SystemRDL 2.0 features
* Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus * Fully synthesizable SystemVerilog. Tested on Xilinx/AMD's Vivado & Intel Quartus
.. warning::
The PeakRDL-regblock SV generator is still in pre-production (v0.x version numbers).
During this time, I may decide to refactor things which could break compatibility.
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