bslathi19/PeakRDL-regblock
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
37 Commits 1 Branch 0 Tags
404e7e83654389b36bae0c38e03cc26adb814a78
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Alex Mykyta 404e7e8365 gh actions
2022-02-25 23:27:01 -08:00
.github/workflows
gh actions
2022-02-25 23:27:01 -08:00
docs
Lint and typing cleanup
2022-02-25 23:23:47 -08:00
peakrdl/regblock
Lint and typing cleanup
2022-02-25 23:23:47 -08:00
test
Lint and typing cleanup
2022-02-25 23:23:47 -08:00
.gitignore
Improve template path handling. Add synthesis tests
2022-02-23 22:53:54 -08:00
LICENSE
initial dev
2021-06-01 21:57:12 -07:00
MANIFEST.in
Add counter support
2021-12-11 20:41:49 -08:00
README.md
gh actions
2022-02-25 23:27:01 -08:00
setup.py
move docs
2021-12-12 18:30:49 -08:00

README.md

Documentation Status build PyPI - Python Version

IMPORTANT

This project has no official releases yet and is still under active development!

PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

Documentation

See the PeakRDL-regblock Documentation for more details

Reference in New Issue View Git Blame Copy Permalink
Description
No description provided
Readme 1.3 MiB
Languages
Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%