14 lines
768 B
Markdown
14 lines
768 B
Markdown
[](http://peakrdl-regblock.readthedocs.io)
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[](https://github.com/SystemRDL/PeakRDL-regblock/actions?query=workflow%3Abuild+branch%3Amain)
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[](https://pypi.org/project/peakrdl-regblock)
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# IMPORTANT
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This project has no official releases yet and is still under active development!
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# PeakRDL-regblock
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Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
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## Documentation
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See the [PeakRDL-regblock Documentation](http://peakrdl-regblock.readthedocs.io) for more details
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