Files
PeakRDL-regblock/peakrdl/regblock/cpuif/base.py
2022-02-23 22:53:54 -08:00

46 lines
1.3 KiB
Python

from typing import TYPE_CHECKING, Optional
import inspect
import os
import jinja2 as jj
from ..utils import get_always_ff_event, clog2, is_pow2
if TYPE_CHECKING:
from ..exporter import RegblockExporter
from systemrdl import SignalNode
class CpuifBase:
# Path is relative to class that defines it
template_path = ""
def __init__(self, exp:'RegblockExporter', cpuif_reset:Optional['SignalNode'], data_width:int=32, addr_width:int=32):
self.exp = exp
self.reset = cpuif_reset
self.data_width = data_width
self.addr_width = addr_width
@property
def port_declaration(self) -> str:
raise NotImplementedError()
def get_implementation(self) -> str:
class_dir = os.path.dirname(inspect.getfile(self.__class__))
loader = jj.FileSystemLoader(class_dir)
jj_env = jj.Environment(
loader=loader,
undefined=jj.StrictUndefined,
)
context = {
"cpuif": self,
"get_always_ff_event": lambda resetsignal : get_always_ff_event(self.exp.dereferencer, resetsignal),
"get_resetsignal": self.exp.dereferencer.get_resetsignal,
"clog2": clog2,
"is_pow2": is_pow2,
}
template = jj_env.get_template(self.template_path)
return template.render(context)