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Maciej Dudek a7cea87d40 Remove unreachable code 
According to the SystemRDL specification interrupt can be either:
level, posedge, negedge, bothedge, or nonsticky.
This means that it's impossible to reach create filed that
satisfies [Pos|Neg|Both]edgeNonstickybit match functions.

Signed-off-by: Maciej Dudek <mdudek@antmicro.com>
2025-04-10 21:45:56 -07:00
.github
drop py3.6. Misc housekeeping
2025-03-03 21:37:07 -08:00
docs
Add FAQ to docs
2025-03-08 18:35:46 -08:00
hdl-src
Add Intel Avalon MM cpuif. #40
2023-05-14 17:00:55 -07:00
src/peakrdl_regblock
Remove unreachable code
2025-04-10 21:45:56 -07:00
tests
Make swmod respect cpuif byte strobes. #137
2025-04-10 21:26:08 -07:00
.gitignore
Reorganize how tb infrstructure selects toolchains
2023-10-22 11:04:43 -07:00
.readthedocs.yaml
Fix hwif type name generation to properly handle parameterized component names. #70
2023-10-11 21:58:10 -07:00
CONTRIBUTING.md
Add contributing guidelines, issue templates, and PR template
2024-05-04 18:04:52 -07:00
LICENSE
initial dev
2021-06-01 21:57:12 -07:00
MANIFEST.in
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
pyproject.toml
drop py3.6. Misc housekeeping
2025-03-03 21:37:07 -08:00
README.md
Add coveralls
2023-03-13 21:47:33 -07:00

README.md

Documentation Status build Coverage Status PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
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Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
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