bslathi19/PeakRDL-regblock
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Paul Roukema cbeb6172a8 Fix "hier" mode hwif generation 
Signed-off-by: Paul Roukema <paul.roukema@fidus.com>
2022-09-12 20:48:42 -07:00
.github/workflows
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
docs
Add pre-production warning
2022-07-29 23:32:15 -07:00
src/peakrdl_regblock
Fix "hier" mode hwif generation
2022-09-12 20:48:42 -07:00
tests
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
.gitignore
Improve template path handling. Add synthesis tests
2022-02-23 22:53:54 -08:00
LICENSE
initial dev
2021-06-01 21:57:12 -07:00
MANIFEST.in
Switch to use regular non-namespaced package
2022-06-09 20:24:53 -07:00
README.md
Update readme
2022-07-30 23:05:21 -07:00
setup.py
Add PeakRDL application entry point hook
2022-07-18 20:28:08 -07:00

README.md

Documentation Status build PyPI - Python Version

PeakRDL-regblock

Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the PeakRDL project.

Documentation

See the PeakRDL-regblock Documentation for more details

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Readme 1.3 MiB
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Python 56.8%
SystemVerilog 42.8%
Tcl 0.3%
Shell 0.1%