46 lines
1.6 KiB
Plaintext
46 lines
1.6 KiB
Plaintext
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================================================================================
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Signal wrapper classes
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================================================================================
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Define a signal wrapper class that is easier to use in templates.
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Provides the following properties:
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.is_async
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.is_activehigh
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.identifier
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Returns the Verilog identifier string for this signal
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.activehigh_identifier
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Normalizes identifier to active-high logic
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same as .identifier, but prepends '~' if is_activehigh = False
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.width
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Default reset class instance:
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Extends the base class
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Hardcodes as follows:
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.is_async = True
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.is_activehigh = True
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.identifier = "rst"
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.width = 1
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Wrapper classes
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Wrap around a systemrdl.SignalNode
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================================================================================
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CPU Interface Class
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================================================================================
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Entry point class for a given CPU interface type (APB, AXI, etc..)
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Does the following:
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- Provide linkage to the logic implementation Jinja template
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- Interface signal identifier properties
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Aliases for signal identifiers to allow flat or sv-interface style
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eg:
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self.psel --> "s_apb_psel" or "s_apb.psel"
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if sv interface, use the interface name class prpoerty
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- Port declaration text property
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declare as sv interface, or flat port list
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If flattened, should use signal identifier properties
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If sv interface, I should breakout the interface & modport name as
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class properties for easy user-override
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