bslathi19/alibaba_pcie
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Update regs

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This commit is contained in:
Byron Lathi
2025-11-23 22:02:53 -08:00
parent e702967e8e
commit 3419fd6a61
7 changed files with 203 additions and 25 deletions
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50
sim/alibaba_pcie.py
View File

@@ -10,6 +10,8 @@ from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
from baser import BaseRSerdesSource, BaseRSerdesSink
from alibaba_pcie_top_regs import alibaba_pcie_top_regsClass
CLK_PERIOD = 4
class TB:
@@ -146,28 +148,36 @@ async def test_sanity(dut):
await mem.write(0, message)
regmap = alibaba_pcie_top_regsClass()
pcie_dma_rd = regmap.pcie_top_regs.pcie_dma_regs.dma_rd
pcie_dma_wr = regmap.pcie_top_regs.pcie_dma_regs.dma_wr
eth_dma_rd = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_rd
eth_dma_wr = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_wr
# DMA from host to dma memory
await dev_bar0.write_dword(0x0, 0x00000000)
await dev_bar0.write_dword(0x4, 0x00000000)
await dev_bar0.write_dword(0x8, 0x00000000)
await dev_bar0.write_dword(0xc, len(message))
await dev_bar0.write_dword(0x10, 0x00000001)
await dev_bar0.write_dword(pcie_dma_rd.src_addr_low.addr, 0x00000000)
await dev_bar0.write_dword(pcie_dma_rd.src_addr_high.addr, 0x00000000)
await dev_bar0.write_dword(pcie_dma_rd.dst_addr.addr, 0x00000000)
await dev_bar0.write_dword(pcie_dma_rd.length.addr, len(message))
await dev_bar0.write_dword(pcie_dma_rd.trigger.addr, 0x00000001)
await Timer(1, "us")
# Set up stream to memory DMA to store ethernet frame
await dev_bar0.write_dword(0x180, 0x00000000)
await dev_bar0.write_dword(0x184, 0x00000000)
await dev_bar0.write_dword(0x188, 0x00000000)
await dev_bar0.write_dword(0x18c, len(message))
await dev_bar0.write_dword(0x190, 0x00000001)
await dev_bar0.write_dword(eth_dma_wr.src_addr.addr, 0x00000000)
await dev_bar0.write_dword(eth_dma_wr.dst_addr_low.addr, 0x00000000)
await dev_bar0.write_dword(eth_dma_wr.dst_addr_high.addr, 0x00000000)
await dev_bar0.write_dword(eth_dma_wr.length.addr, len(message))
await dev_bar0.write_dword(eth_dma_wr.trigger.addr, 0x00000001)
# Trigger memory to stream dma to send ethernet frame
await dev_bar0.write_dword(0x1a0, 0x00000000)
await dev_bar0.write_dword(0x1a4, 0x00000000)
await dev_bar0.write_dword(0x1a8, 0x00000000)
await dev_bar0.write_dword(0x1ac, len(message))
await dev_bar0.write_dword(0x1b0, 0x00000001)
await dev_bar0.write_dword(eth_dma_rd.src_addr_low.addr, 0x00000000)
await dev_bar0.write_dword(eth_dma_rd.src_addr_high.addr, 0x00000000)
await dev_bar0.write_dword(eth_dma_rd.dst_addr.addr, 0x00000000)
await dev_bar0.write_dword(eth_dma_rd.length.addr, len(message))
await dev_bar0.write_dword(eth_dma_rd.trigger.addr, 0x00000001)
rx_frame = await tb.serdes_sinks[0].recv()
@@ -178,11 +188,11 @@ async def test_sanity(dut):
await Timer(1, "us")
# DMA from dma memory to host
await dev_bar0.write_dword(0x20, 0x00000100)
await dev_bar0.write_dword(0x24, 0x00000000)
await dev_bar0.write_dword(0x28, 0x00000000)
await dev_bar0.write_dword(0x2c, len(message))
await dev_bar0.write_dword(0x30, 0x00000001)
await dev_bar0.write_dword(pcie_dma_wr.src_addr.addr, 0x00000000)
await dev_bar0.write_dword(pcie_dma_wr.dst_addr_low.addr, 0x00000000)
await dev_bar0.write_dword(pcie_dma_wr.dst_addr_high.addr, 0x00000000)
await dev_bar0.write_dword(pcie_dma_wr.length.addr, len(message))
await dev_bar0.write_dword(pcie_dma_wr.trigger.addr, 0x00000001)
await Timer(1, "us")

1
sim/alibaba_pcie_top_regs.py Symbolic link
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@@ -0,0 +1 @@
../src/regs/alibaba_pcie_top_regs.py