bslathi19/alibaba_pcie
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Update regs

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This commit is contained in:
Byron Lathi
2025-11-23 22:02:53 -08:00
parent e702967e8e
commit 3419fd6a61
7 changed files with 203 additions and 25 deletions
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165
src/regs/alibaba_pcie_top_regs.py Normal file
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@@ -0,0 +1,165 @@
class AddrNode():
addr: int
class alibaba_pcie_top_regsClass(AddrNode):
class pcie_top_regsClass(AddrNode):
class pcie_dma_regsClass(AddrNode):
class dma_rdClass(AddrNode):
class src_addr_lowClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class src_addr_highClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class dst_addrClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class lengthClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class triggerClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class doneClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
def __init__(self, addr: int = 0):
self.addr = addr
self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
self.src_addr_high = self.src_addr_highClass(self.addr + 4)
self.dst_addr = self.dst_addrClass(self.addr + 8)
self.length = self.lengthClass(self.addr + 12)
self.trigger = self.triggerClass(self.addr + 16)
self.done = self.doneClass(self.addr + 20)
class dma_wrClass(AddrNode):
class dst_addr_lowClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class dst_addr_highClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class src_addrClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class lengthClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class triggerClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class doneClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
def __init__(self, addr: int = 0):
self.addr = addr
self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
self.src_addr = self.src_addrClass(self.addr + 8)
self.length = self.lengthClass(self.addr + 12)
self.trigger = self.triggerClass(self.addr + 16)
self.done = self.doneClass(self.addr + 20)
def __init__(self, addr: int = 0):
self.addr = addr
self.dma_rd = self.dma_rdClass(self.addr + 0)
self.dma_wr = self.dma_wrClass(self.addr + 32)
def __init__(self, addr: int = 0):
self.addr = addr
self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 0)
class eth_dma_wrapper_regsClass(AddrNode):
class eth_mac_25g_us_regsClass(AddrNode):
class commonClass(AddrNode):
class xcvr_gtpowergood_outClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class xcvr_qpll0lock_outClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class xcvr_qpll1lock_outClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
def __init__(self, addr: int = 0):
self.addr = addr
self.xcvr_gtpowergood_out = self.xcvr_gtpowergood_outClass(self.addr + 0)
self.xcvr_qpll0lock_out = self.xcvr_qpll0lock_outClass(self.addr + 4)
self.xcvr_qpll1lock_out = self.xcvr_qpll1lock_outClass(self.addr + 8)
class lanesClass(AddrNode):
class rx_block_lockClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class rx_statusClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
def __init__(self, addr: int = 0):
self.addr = addr
self.rx_block_lock = self.rx_block_lockClass(self.addr + 0)
self.rx_status = self.rx_statusClass(self.addr + 4)
def __init__(self, addr: int = 0):
self.addr = addr
self.common = self.commonClass(self.addr + 0)
self.lanes = [self.lanesClass(self.addr + 32 + 8*i) for i in range(2)]
class pcie_dma_regsClass(AddrNode):
class dma_rdClass(AddrNode):
class src_addr_lowClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class src_addr_highClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class dst_addrClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class lengthClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class triggerClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class doneClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
def __init__(self, addr: int = 0):
self.addr = addr
self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
self.src_addr_high = self.src_addr_highClass(self.addr + 4)
self.dst_addr = self.dst_addrClass(self.addr + 8)
self.length = self.lengthClass(self.addr + 12)
self.trigger = self.triggerClass(self.addr + 16)
self.done = self.doneClass(self.addr + 20)
class dma_wrClass(AddrNode):
class dst_addr_lowClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class dst_addr_highClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class src_addrClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class lengthClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class triggerClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
class doneClass(AddrNode):
def __init__(self, addr: int = 0):
self.addr = addr
def __init__(self, addr: int = 0):
self.addr = addr
self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
self.src_addr = self.src_addrClass(self.addr + 8)
self.length = self.lengthClass(self.addr + 12)
self.trigger = self.triggerClass(self.addr + 16)
self.done = self.doneClass(self.addr + 20)
def __init__(self, addr: int = 0):
self.addr = addr
self.dma_rd = self.dma_rdClass(self.addr + 0)
self.dma_wr = self.dma_wrClass(self.addr + 32)
def __init__(self, addr: int = 0):
self.addr = addr
self.eth_mac_25g_us_regs = self.eth_mac_25g_us_regsClass(self.addr + 0)
self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 128)
def __init__(self, addr: int = 0):
self.addr = addr
self.pcie_top_regs = self.pcie_top_regsClass(self.addr + 0)
self.eth_dma_wrapper_regs = self.eth_dma_wrapper_regsClass(self.addr + 256)

4
src/regs/alibaba_pcie_top_regs.sv
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@@ -3,8 +3,8 @@
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Date: 2025-11-23
// Version: 0.6.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================

4
src/regs/alibaba_pcie_top_regs_pkg.sv
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@@ -3,8 +3,8 @@
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Date: 2025-11-23
// Version: 0.6.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================

3
src/regs/compile_regs.sh
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@@ -1,3 +1,4 @@
SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb
peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb
peakrdl python-regmap -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.py