bslathi19/alibaba_pcie
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Use taxi apb interface, finish reorg

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This commit is contained in:
Byron Lathi
2025-11-22 16:07:56 -08:00
parent de33a46c78
commit 85cb3cc2a6
13 changed files with 209 additions and 230 deletions
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2
src/pcie/regs/compile_regs.sh
View File

@@ -1,2 +1,2 @@
peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif taxi-apb

81
src/pcie/regs/pcie_top_regs.sv
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@@ -11,30 +11,8 @@
module pcie_top_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [5:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_pcie_dma_regs_PCLK,
output logic m_apb_pcie_dma_regs_PRESETn,
output logic m_apb_pcie_dma_regs_PSEL,
output logic m_apb_pcie_dma_regs_PENABLE,
output logic m_apb_pcie_dma_regs_PWRITE,
output logic [5:0] m_apb_pcie_dma_regs_PADDR,
output logic [2:0] m_apb_pcie_dma_regs_PPROT,
output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
input logic [31:0] m_apb_pcie_dma_regs_PRDATA,
input logic m_apb_pcie_dma_regs_PREADY,
input logic m_apb_pcie_dma_regs_PSLVERR
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_pcie_dma_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
@@ -68,31 +46,46 @@ module pcie_top_regs (
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
end
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.PSTRB;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.penable = s_apb.penable;
assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
@@ -102,11 +95,11 @@ module pcie_top_regs (
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
end
end