bslathi19/alibaba_pcie
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This commit is contained in:
Byron Lathi
2025-11-22 12:30:57 -08:00
parent 0de33aaa1b
commit de33a46c78
27 changed files with 1363 additions and 177 deletions
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2
requirements.txt
View File

@@ -7,4 +7,4 @@ rtl-manifest
build_fpga
fpga-sim
peakrdl
git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@dev/downsize_apb_paddr

4
sources.list
View File

@@ -9,5 +9,7 @@ src/regs/verilator.vlt
src/regs/pcie_dma_regs_pkg.sv
src/regs/pcie_dma_regs.sv
src/pcie_dma_wrapper.sv
src/eth_dma_wrapper.sv
src/eth/regs/eth_mac_25g_us_regs_pkg.sv
src/eth/regs/eth_mac_25g_us_regs.sv
src/eth/eth_dma_wrapper.sv
sub/taxi_sources.list

159
src/alibaba_pcie_top.sv
View File

@@ -43,45 +43,12 @@ module alibaba_pcie(
logic clk_pcie_gt;
logic clk_pcie;
logic rst_pcie;
logic clk_250;
logic rst_250;
logic user_lnk_up;
logic phy_rdy_out;
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
taxi_axil_if m_axil_rd();
taxi_axil_if m_axil_wr();
taxi_apb_if #(.ADDR_W(7)) s_apb();
taxi_apb_if #(.ADDR_W(9)) s_apb();
taxi_apb_if #(.ADDR_W(6)) m_apb[2]();
`ifndef SIM
IBUFDS_GTE4 m_ibufds (
.CEB('0),
.I(pcie_mgt_refclk_p),
.IB(pcie_mgt_refclk_n),
.O(clk_pcie_gt),
.ODIV2(clk_pcie)
);
`endif
assign Led_o[0] = user_lnk_up;
assign Led_o[1] = phy_rdy_out;
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
taxi_apb_if #(.ADDR_W(9)) m_apb[2]();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
@@ -102,43 +69,6 @@ taxi_apb_interconnect #(
.m_apb (m_apb)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_tx_psdpram (
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_pcie_wr_if),
.dma_ram_rd (dma_ram_eth_rd_if)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_rx_psdpram(
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_eth_wr_if),
.dma_ram_rd (dma_ram_pcie_rd_if)
);
taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
.clk (clk_250),
.rst (rst_250),
.s_axis_cq (m_axis_cq),
.m_axis_cc (s_axis_cc),
.m_axil_wr (m_axil_wr),
.m_axil_rd (m_axil_rd),
.completer_id ('0),
.completer_id_en ('0),
.stat_err_cor (),
.stat_err_uncor ()
);
taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
.clk (clk_250),
@@ -150,18 +80,6 @@ taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
.m_apb (s_apb)
);
pcie_dma_wrapper u_pcie_dma_wrapper (
.clk (clk_250),
.rst (rst_250),
.m_axis_rq (s_axis_rq),
.s_axis_rc (m_axis_rc),
.wr_dma_mst (dma_ram_pcie_wr_if),
.rd_dma_mst (dma_ram_pcie_rd_if),
.s_apb (m_apb[0])
);
eth_dma_wrapper u_eth_dma_wrapper (
.clk_250 (clk_250),
@@ -181,70 +99,25 @@ eth_dma_wrapper u_eth_dma_wrapper (
.s_apb (m_apb[1])
);
`ifndef SIM
pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
.pci_exp_txn(pci_exp_txn),
.pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn),
.pci_exp_rxp(pci_exp_rxp),
pcie_top u_pcie_top(
.pcie_exp_rxp (pcie_exp_rxp)
.pcie_exp_rxn (pcie_exp_rxn)
.pcie_exp_txp (pcie_exp_txp)
.pcie_exp_txn (pcie_exp_txn),
.user_clk(clk_250),
.user_reset(rst_250),
.user_lnk_up(user_lnk_up),
.pcie_mgt_refclk_p (pcie_mgt_refclk_p),
.pcie_mgt_refclk_n (pcie_mgt_refclk_n),
.s_axis_rq_tdata(s_axis_rq.tdata),
.s_axis_rq_tkeep(s_axis_rq.tkeep),
.s_axis_rq_tlast(s_axis_rq.tlast),
.s_axis_rq_tready(s_axis_rq.tready),
.s_axis_rq_tuser(s_axis_rq.tuser),
.s_axis_rq_tvalid(s_axis_rq.tvalid),
.pcie_reset_n (pcie_reset_n),
.m_axis_rc_tdata(m_axis_rc.tdata),
.m_axis_rc_tkeep(m_axis_rc.tkeep),
.m_axis_rc_tlast(m_axis_rc.tlast),
.m_axis_rc_tready(m_axis_rc.tready),
.m_axis_rc_tuser(m_axis_rc.tuser),
.m_axis_rc_tvalid(m_axis_rc.tvalid),
.user_lnk_up (Led_o[0]),
.phy_rdy_out (Led_o[1]),
.m_axis_cq_tdata(m_axis_cq.tdata),
.m_axis_cq_tkeep(m_axis_cq.tkeep),
.m_axis_cq_tlast(m_axis_cq.tlast),
.m_axis_cq_tready(m_axis_cq.tready),
.m_axis_cq_tuser(m_axis_cq.tuser),
.m_axis_cq_tvalid(m_axis_cq.tvalid),
.dma_ram_eth_wr_if (dma_ram_eth_wr_if),
.dma_ram_eth_rd_if (dma_ram_eth_rd_if),
.s_axis_cc_tdata(s_axis_cc.tdata),
.s_axis_cc_tkeep(s_axis_cc.tkeep),
.s_axis_cc_tlast(s_axis_cc.tlast),
.s_axis_cc_tready(s_axis_cc.tready),
.s_axis_cc_tuser(s_axis_cc.tuser),
.s_axis_cc_tvalid(s_axis_cc.tvalid),
.cfg_interrupt_int('0),
.cfg_interrupt_pending(),
.cfg_interrupt_sent('0),
.cfg_interrupt_msi_enable(),
.cfg_interrupt_msi_mmenable(),
.cfg_interrupt_msi_mask_update(),
.cfg_interrupt_msi_data(),
.cfg_interrupt_msi_select('0),
.cfg_interrupt_msi_int('0),
.cfg_interrupt_msi_pending_status('0),
.cfg_interrupt_msi_pending_status_data_enable('0),
.cfg_interrupt_msi_pending_status_function_num('0),
.cfg_interrupt_msi_sent(),
.cfg_interrupt_msi_fail(),
.cfg_interrupt_msi_attr('0),
.cfg_interrupt_msi_tph_present('0),
.cfg_interrupt_msi_tph_type('0),
.cfg_interrupt_msi_tph_st_tag('0),
.cfg_interrupt_msi_function_number('0),
.sys_clk(clk_pcie),
.sys_clk_gt(clk_pcie_gt),
.sys_reset(pcie_reset_n),
.phy_rdy_out(phy_rdy_out)
.m_axil_rd (m_axil_rd),
.m_axil_wr (m_axil_wr)
);
`endif
endmodule

94
src/eth_dma_wrapper.sv → src/eth/eth_dma_wrapper.sv
View File

@@ -84,6 +84,40 @@ endgenerate
taxi_axis_if axis_sfp_stat();
eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in;
eth_mac_25g_us_regs u_eth_mac_25g_us_regs (
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (s_apb_eth.psel),
.s_apb_penable (s_apb_eth.penable),
.s_apb_pwrite (s_apb_eth.pwrite),
.s_apb_pprot (s_apb_eth.pprot),
.s_apb_paddr (s_apb_eth.paddr),
.s_apb_pwdata (s_apb_eth.pwdata),
.s_apb_pstrb (s_apb_eth.pstrb),
.s_apb_pready (s_apb_eth.pready),
.s_apb_prdata (s_apb_eth.prdata),
.s_apb_pslverr (s_apb_eth.pslverr),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
);
assign hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
logic rx_block_lock[2];
logic rx_status[2];
always_comb begin
for (int i = 0; i < 2; i++) begin
assign hwif_in.lane[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
assign hwif_in.lane[i].rx_status.rx_status.next = rx_status[i];
end
end
taxi_eth_mac_25g_us #(
`ifdef SIM
.SIM('1),
@@ -106,14 +140,14 @@ taxi_eth_mac_25g_us #(
.xcvr_qpll0pd_in (1'b0),
.xcvr_qpll0reset_in (1'b0),
.xcvr_qpll0pcierate_in (3'd0),
.xcvr_qpll0lock_out (),
.xcvr_qpll0lock_out (hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next),
.xcvr_qpll0clk_out (),
.xcvr_qpll0refclk_out (),
.xcvr_gtrefclk01_in (sfp_mgt_refclk),
.xcvr_qpll1pd_in (1'b0),
.xcvr_qpll1reset_in (1'b0),
.xcvr_qpll1pcierate_in (3'd0),
.xcvr_qpll1lock_out (),
.xcvr_qpll1lock_out (hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next),
.xcvr_qpll1clk_out (),
.xcvr_qpll1refclk_out (),
@@ -176,9 +210,9 @@ taxi_eth_mac_25g_us #(
.stat_tx_err_underflow (),
.rx_start_packet (),
.rx_error_count (),
.rx_block_lock (),
.rx_block_lock (rx_block_lock),
.rx_high_ber (),
.rx_status (),
.rx_status (rx_status),
.stat_rx_byte (),
.stat_rx_pkt_len (),
.stat_rx_pkt_fragment (),
@@ -259,26 +293,26 @@ taxi_eth_mac_25g_us #(
taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) rd_desc();
taxi_dma_desc_if #(.SRC_ADDR_W(16), .DST_ADDR_W(16), .ID_W(8), .DEST_W(8)) wr_desc();
pcie_dma_regs_pkg::pcie_dma_regs__in_t hwif_in;
pcie_dma_regs_pkg::pcie_dma_regs__out_t hwif_out;
pcie_dma_regs_pkg::pcie_dma_regs__in_t dma_hwif_in;
pcie_dma_regs_pkg::pcie_dma_regs__out_t dma_hwif_out;
pcie_dma_regs u_pcie_dma_regs(
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (s_apb.psel),
.s_apb_penable (s_apb.penable),
.s_apb_pwrite (s_apb.pwrite),
.s_apb_pprot (s_apb.pprot),
.s_apb_paddr (s_apb.paddr),
.s_apb_pwdata (s_apb.pwdata),
.s_apb_pstrb (s_apb.pstrb),
.s_apb_pready (s_apb.pready),
.s_apb_prdata (s_apb.prdata),
.s_apb_pslverr (s_apb.pslverr),
.s_apb_psel (s_apb_dma.psel),
.s_apb_penable (s_apb_dma.penable),
.s_apb_pwrite (s_apb_dma.pwrite),
.s_apb_pprot (s_apb_dma.pprot),
.s_apb_paddr (s_apb_dma.paddr),
.s_apb_pwdata (s_apb_dma.pwdata),
.s_apb_pstrb (s_apb_dma.pstrb),
.s_apb_pready (s_apb_dma.pready),
.s_apb_prdata (s_apb_dma.prdata),
.s_apb_pslverr (s_apb_dma.pslverr),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
.hwif_in (dma_hwif_in),
.hwif_out (dma_hwif_out)
);
logic [7:0] read_tag;
@@ -300,35 +334,35 @@ end
always_comb begin
rd_desc.req_src_addr = hwif_out.dma_rd.src_addr_low.addr.value[15:0];
rd_desc.req_src_addr = dma_hwif_out.dma_rd.src_addr_low.addr.value[15:0];
rd_desc.req_src_sel = '0;
rd_desc.req_dst_addr = hwif_out.dma_rd.dst_addr.addr.value;
rd_desc.req_dst_addr = dma_hwif_out.dma_rd.dst_addr.addr.value;
rd_desc.req_dst_sel = '0;
rd_desc.req_imm = '0;
rd_desc.req_imm_en = '0;
rd_desc.req_len = hwif_out.dma_rd.length.len.value;
rd_desc.req_len = dma_hwif_out.dma_rd.length.len.value;
rd_desc.req_tag = read_tag;
rd_desc.req_id = '0;
rd_desc.req_dest = '0;
rd_desc.req_user = '0;
rd_desc.req_valid = hwif_out.dma_rd.trigger.trigger.value;
hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
rd_desc.req_valid = dma_hwif_out.dma_rd.trigger.trigger.value;
dma_hwif_in.dma_rd.trigger.trigger.hwclr = (rd_desc.req_valid && rd_desc.req_ready);
dma_hwif_in.dma_rd.done.done.hwset = rd_desc.sts_valid;
wr_desc.req_src_addr = hwif_out.dma_wr.src_addr.addr.value;
wr_desc.req_src_addr = dma_hwif_out.dma_wr.src_addr.addr.value;
wr_desc.req_src_sel = '0;
wr_desc.req_dst_addr = hwif_out.dma_wr.dst_addr_low.addr.value[15:0];
wr_desc.req_dst_addr = dma_hwif_out.dma_wr.dst_addr_low.addr.value[15:0];
wr_desc.req_dst_sel = '0;
wr_desc.req_imm = '0;
wr_desc.req_imm_en = '0;
wr_desc.req_len = hwif_out.dma_wr.length.len.value;
wr_desc.req_len = dma_hwif_out.dma_wr.length.len.value;
wr_desc.req_tag = write_tag;
wr_desc.req_id = '0;
wr_desc.req_dest = '0;
wr_desc.req_user = '0;
wr_desc.req_valid = hwif_out.dma_wr.trigger.trigger.value;
hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
wr_desc.req_valid = dma_hwif_out.dma_wr.trigger.trigger.value;
dma_hwif_in.dma_wr.trigger.trigger.hwclr = (wr_desc.req_valid && wr_desc.req_ready);
dma_hwif_in.dma_wr.done.done.hwset = wr_desc.sts_valid;
end
// 250 is too slow to actually saturate 25Gbps, but

168
src/eth/pcie_top.sv Normal file
View File

@@ -0,0 +1,168 @@
module pcie_top(
input wire [7:0] pci_exp_rxp,
input wire [7:0] pci_exp_rxn,
output wire [7:0] pci_exp_txp,
output wire [7:0] pci_exp_txn,
input wire pcie_mgt_refclk_p,
input wire pcie_mgt_refclk_n,
input wire pcie_reset_n,
output wire user_lnk_up,
output wire phy_rdy_out,
taxi_dma_ram_if.wr_slv dma_ram_eth_wr_if,
taxi_dma_ram_if.rd_slv dma_ram_eth_rd_if,
taxi_axil_if.rd_mst m_axil_rd,
taxi_axil_if.wr_mst m_axil_wr
);
logic clk_pcie_gt;
logic clk_pcie;
logic rst_pcie;
logic clk_250;
logic rst_250;
logic user_lnk_up;
logic phy_rdy_out;
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(62), .KEEP_W(8)) s_axis_rq();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
`ifndef SIM
IBUFDS_GTE4 m_ibufds (
.CEB('0),
.I(pcie_mgt_refclk_p),
.IB(pcie_mgt_refclk_n),
.O(clk_pcie_gt),
.ODIV2(clk_pcie)
);
`endif
taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
.clk (clk_250),
.rst (rst_250),
.s_axis_cq (m_axis_cq),
.m_axis_cc (s_axis_cc),
.m_axil_wr (m_axil_wr),
.m_axil_rd (m_axil_rd),
.completer_id ('0),
.completer_id_en ('0),
.stat_err_cor (),
.stat_err_uncor ()
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_tx_psdpram (
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_pcie_wr_if),
.dma_ram_rd (dma_ram_eth_rd_if)
);
taxi_dma_psdpram #(
.SIZE(16384)
) u_taxi_dma_rx_psdpram(
.clk (clk_250),
.rst (rst_250),
.dma_ram_wr (dma_ram_eth_wr_if),
.dma_ram_rd (dma_ram_pcie_rd_if)
);
pcie_dma_wrapper u_pcie_dma_wrapper (
.clk (clk_250),
.rst (rst_250),
.m_axis_rq (s_axis_rq),
.s_axis_rc (m_axis_rc),
.wr_dma_mst (dma_ram_pcie_wr_if),
.rd_dma_mst (dma_ram_pcie_rd_if),
.s_apb (m_apb[0])
);
`ifndef SIM
pcie4_uscale_plus_0 u_pcie4_uscale_plus_0 (
.pci_exp_txn(pci_exp_txn),
.pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn),
.pci_exp_rxp(pci_exp_rxp),
.user_clk(clk_250),
.user_reset(rst_250),
.user_lnk_up(user_lnk_up),
.s_axis_rq_tdata(s_axis_rq.tdata),
.s_axis_rq_tkeep(s_axis_rq.tkeep),
.s_axis_rq_tlast(s_axis_rq.tlast),
.s_axis_rq_tready(s_axis_rq.tready),
.s_axis_rq_tuser(s_axis_rq.tuser),
.s_axis_rq_tvalid(s_axis_rq.tvalid),
.m_axis_rc_tdata(m_axis_rc.tdata),
.m_axis_rc_tkeep(m_axis_rc.tkeep),
.m_axis_rc_tlast(m_axis_rc.tlast),
.m_axis_rc_tready(m_axis_rc.tready),
.m_axis_rc_tuser(m_axis_rc.tuser),
.m_axis_rc_tvalid(m_axis_rc.tvalid),
.m_axis_cq_tdata(m_axis_cq.tdata),
.m_axis_cq_tkeep(m_axis_cq.tkeep),
.m_axis_cq_tlast(m_axis_cq.tlast),
.m_axis_cq_tready(m_axis_cq.tready),
.m_axis_cq_tuser(m_axis_cq.tuser),
.m_axis_cq_tvalid(m_axis_cq.tvalid),
.s_axis_cc_tdata(s_axis_cc.tdata),
.s_axis_cc_tkeep(s_axis_cc.tkeep),
.s_axis_cc_tlast(s_axis_cc.tlast),
.s_axis_cc_tready(s_axis_cc.tready),
.s_axis_cc_tuser(s_axis_cc.tuser),
.s_axis_cc_tvalid(s_axis_cc.tvalid),
.cfg_interrupt_int('0),
.cfg_interrupt_pending(),
.cfg_interrupt_sent('0),
.cfg_interrupt_msi_enable(),
.cfg_interrupt_msi_mmenable(),
.cfg_interrupt_msi_mask_update(),
.cfg_interrupt_msi_data(),
.cfg_interrupt_msi_select('0),
.cfg_interrupt_msi_int('0),
.cfg_interrupt_msi_pending_status('0),
.cfg_interrupt_msi_pending_status_data_enable('0),
.cfg_interrupt_msi_pending_status_function_num('0),
.cfg_interrupt_msi_sent(),
.cfg_interrupt_msi_fail(),
.cfg_interrupt_msi_attr('0),
.cfg_interrupt_msi_tph_present('0),
.cfg_interrupt_msi_tph_type('0),
.cfg_interrupt_msi_tph_st_tag('0),
.cfg_interrupt_msi_function_number('0),
.sys_clk(clk_pcie),
.sys_clk_gt(clk_pcie_gt),
.sys_reset(pcie_reset_n),
.phy_rdy_out(phy_rdy_out)
);
`endif
endmodule

2
src/eth/regs/compile_regs.sh Executable file
View File

@@ -0,0 +1,2 @@
peakrdl regblock -t eth_mac_25g_us_regs eth_mac_25g_us_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl -o . --cpuif apb4-flat

5
src/eth/regs/eth_dma_wrapper_regs.rdl Normal file
View File

@@ -0,0 +1,5 @@
addrmap eth_dma_wrapper_regs {
external eth_mac_25g_us_regs eth_mac_25g_us_regs @ 0x0;
external pcie_dma_regs pcie_dma_regs @ 0x80;
};

185
src/eth/regs/eth_dma_wrapper_regs.sv Normal file
View File

@@ -0,0 +1,185 @@
//==========================================================
// Module: eth_dma_wrapper_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module eth_dma_wrapper_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [7:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_eth_mac_25g_us_regs_PCLK,
output logic m_apb_eth_mac_25g_us_regs_PRESETn,
output logic m_apb_eth_mac_25g_us_regs_PSEL,
output logic m_apb_eth_mac_25g_us_regs_PENABLE,
output logic m_apb_eth_mac_25g_us_regs_PWRITE,
output logic [6:0] m_apb_eth_mac_25g_us_regs_PADDR,
output logic [2:0] m_apb_eth_mac_25g_us_regs_PPROT,
output logic [31:0] m_apb_eth_mac_25g_us_regs_PWDATA,
output logic [3:0] m_apb_eth_mac_25g_us_regs_PSTRB,
input logic [31:0] m_apb_eth_mac_25g_us_regs_PRDATA,
input logic m_apb_eth_mac_25g_us_regs_PREADY,
input logic m_apb_eth_mac_25g_us_regs_PSLVERR,
output logic m_apb_pcie_dma_regs_PCLK,
output logic m_apb_pcie_dma_regs_PRESETn,
output logic m_apb_pcie_dma_regs_PSEL,
output logic m_apb_pcie_dma_regs_PENABLE,
output logic m_apb_pcie_dma_regs_PWRITE,
output logic [5:0] m_apb_pcie_dma_regs_PADDR,
output logic [2:0] m_apb_pcie_dma_regs_PPROT,
output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
input logic [31:0] m_apb_pcie_dma_regs_PRDATA,
input logic m_apb_pcie_dma_regs_PREADY,
input logic m_apb_pcie_dma_regs_PSLVERR
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [7:0] cpuif_wr_addr;
logic [7:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic eth_mac_25g_us_regs;
logic pcie_dma_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_eth_mac_25g_us_regs_PSEL = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs_PENABLE = s_apb_PENABLE;
assign m_apb_eth_mac_25g_us_regs_PWRITE = cpuif_wr_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs_PADDR = s_apb_PADDR[6:0];
assign m_apb_eth_mac_25g_us_regs_PPROT = s_apb_PPROT;
assign m_apb_eth_mac_25g_us_regs_PWDATA = cpuif_wr_data;
assign m_apb_eth_mac_25g_us_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.eth_mac_25g_us_regs || cpuif_wr_sel.eth_mac_25g_us_regs) begin
cpuif_rd_ack = m_apb_eth_mac_25g_us_regs_PREADY;
cpuif_rd_err = m_apb_eth_mac_25g_us_regs_PSLVERR;
end
if (cpuif_rd_sel.eth_mac_25g_us_regs) begin
cpuif_rd_data = m_apb_eth_mac_25g_us_regs_PRDATA;
end
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (8'h60))) begin
cpuif_wr_sel.eth_mac_25g_us_regs = 1'b1;
end
else if ((cpuif_wr_addr >= (8'h80)) && (cpuif_wr_addr < (8'hb8))) begin
cpuif_wr_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (8'h60))) begin
cpuif_rd_sel.eth_mac_25g_us_regs = 1'b1;
end
else if ((cpuif_rd_addr >= (8'h80)) && (cpuif_rd_addr < (8'hb8))) begin
cpuif_rd_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

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src/eth/regs/eth_dma_wrapper_regs_pkg.sv Normal file
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//==========================================================
// Package: eth_dma_wrapper_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package eth_dma_wrapper_regs_pkg;
localparam ETH_DMA_WRAPPER_REGS_DATA_WIDTH = 32;
localparam ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH = 8;
localparam ETH_DMA_WRAPPER_REGS_SIZE = 'hb8;
localparam ETH_DMA_WRAPPER_REGS_ETH_MAC_25G_US_REGS_ADDR_WIDTH = 7;
localparam ETH_DMA_WRAPPER_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
endpackage

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src/eth/regs/eth_mac_25g_us_regs.rdl Normal file
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addrmap eth_mac_25g_us_regs {
name = "";
desc = "";
regfile {
reg {
name = "xcvr_gtpowergood_out";
desc = "";
field {
name = "xcvr_gtpowergood_out";
desc = "";
hw = w;
sw = r;
} xcvr_gtpowergood_out[0:0] = 0x0;
} xcvr_gtpowergood_out @ 0x0;
reg {
name = "xcvr_qpll0lock_out";
desc = "";
field {
name = "xcvr_qpll0lock_out";
desc = "";
hw = w;
sw = r;
} xcvr_qpll0lock_out[0:0] = 0x0;
} xcvr_qpll0lock_out @ 0x4;
reg {
name = "xcvr_qpll1lock_out";
desc = "";
field {
name = "xcvr_qpll1lock_out";
desc = "";
hw = w;
sw = r;
} xcvr_qpll1lock_out[0:0] = 0x0;
} xcvr_qpll1lock_out @ 0x8;
} common @0x0;
regfile lane {
reg {
name = "rx_block_lock";
desc = "";
field {
name = "rx_block_lock";
desc = "";
hw = w;
sw = r;
} rx_block_lock[0:0] = 0x0;
} rx_block_lock @ 0x0;
reg {
name = "rx_status";
desc = "";
field {
name = "rx_status";
desc = "";
hw = w;
sw = r;
} rx_status[0:0] = 0x0;
} rx_status @ 0x4;
};
lane lanes[2] @ 0x20 += 0x20;
};

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src/eth/regs/eth_mac_25g_us_regs.sv Normal file
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// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module eth_mac_25g_us_regs (
input wire clk,
input wire rst,
input wire s_apb_psel,
input wire s_apb_penable,
input wire s_apb_pwrite,
input wire [2:0] s_apb_pprot,
input wire [6:0] s_apb_paddr,
input wire [31:0] s_apb_pwdata,
input wire [3:0] s_apb_pstrb,
output logic s_apb_pready,
output logic [31:0] s_apb_prdata,
output logic s_apb_pslverr,
input eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [6:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
logic cpuif_req_stall_rd;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
logic cpuif_wr_ack;
logic cpuif_wr_err;
// Request
logic is_active;
always_ff @(posedge clk) begin
if(rst) begin
is_active <= '0;
cpuif_req <= '0;
cpuif_req_is_wr <= '0;
cpuif_addr <= '0;
cpuif_wr_data <= '0;
cpuif_wr_biten <= '0;
end else begin
if(~is_active) begin
if(s_apb_psel) begin
is_active <= '1;
cpuif_req <= '1;
cpuif_req_is_wr <= s_apb_pwrite;
cpuif_addr <= {s_apb_paddr[6:2], 2'b0};
cpuif_wr_data <= s_apb_pwdata;
for(int i=0; i<4; i++) begin
cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
end
end
end else begin
cpuif_req <= '0;
if(cpuif_rd_ack || cpuif_wr_ack) begin
is_active <= '0;
end
end
end
end
// Response
assign s_apb_pready = cpuif_rd_ack | cpuif_wr_ack;
assign s_apb_prdata = cpuif_rd_data;
assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err;
logic cpuif_req_masked;
// Read & write latencies are balanced. Stalls not required
assign cpuif_req_stall_rd = '0;
assign cpuif_req_stall_wr = '0;
assign cpuif_req_masked = cpuif_req
& !(!cpuif_req_is_wr & cpuif_req_stall_rd)
& !(cpuif_req_is_wr & cpuif_req_stall_wr);
//--------------------------------------------------------------------------
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
struct {
logic xcvr_gtpowergood_out;
logic xcvr_qpll0lock_out;
logic xcvr_qpll1lock_out;
} common;
struct {
logic rx_block_lock;
logic rx_status;
} lanes[2];
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_err;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
logic [31:0] decoded_wr_biten;
always_comb begin
automatic logic is_valid_addr;
automatic logic is_invalid_rw;
is_valid_addr = '1; // No error checking on valid address access
is_invalid_rw = '0;
decoded_reg_strb.common.xcvr_gtpowergood_out = cpuif_req_masked & (cpuif_addr == 7'h0) & !cpuif_req_is_wr;
decoded_reg_strb.common.xcvr_qpll0lock_out = cpuif_req_masked & (cpuif_addr == 7'h4) & !cpuif_req_is_wr;
decoded_reg_strb.common.xcvr_qpll1lock_out = cpuif_req_masked & (cpuif_addr == 7'h8) & !cpuif_req_is_wr;
for(int i0=0; i0<2; i0++) begin
decoded_reg_strb.lanes[i0].rx_block_lock = cpuif_req_masked & (cpuif_addr == 7'h20 + (7)'(i0) * 7'h20) & !cpuif_req_is_wr;
decoded_reg_strb.lanes[i0].rx_status = cpuif_req_masked & (cpuif_addr == 7'h24 + (7)'(i0) * 7'h20) & !cpuif_req_is_wr;
end
decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req;
end
// Pass down signals to next stage
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
// Writes are always granted with no error response
assign cpuif_wr_err = '0;
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
logic readback_err;
logic readback_done;
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[7];
assign readback_array[0][0:0] = (decoded_reg_strb.common.xcvr_gtpowergood_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next : '0;
assign readback_array[0][31:1] = '0;
assign readback_array[1][0:0] = (decoded_reg_strb.common.xcvr_qpll0lock_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next : '0;
assign readback_array[1][31:1] = '0;
assign readback_array[2][0:0] = (decoded_reg_strb.common.xcvr_qpll1lock_out && !decoded_req_is_wr) ? hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next : '0;
assign readback_array[2][31:1] = '0;
for(genvar i0=0; i0<2; i0++) begin
assign readback_array[i0 * 2 + 3][0:0] = (decoded_reg_strb.lanes[i0].rx_block_lock && !decoded_req_is_wr) ? hwif_in.lanes[i0].rx_block_lock.rx_block_lock.next : '0;
assign readback_array[i0 * 2 + 3][31:1] = '0;
assign readback_array[i0 * 2 + 4][0:0] = (decoded_reg_strb.lanes[i0].rx_status && !decoded_req_is_wr) ? hwif_in.lanes[i0].rx_status.rx_status.next : '0;
assign readback_array[i0 * 2 + 4][31:1] = '0;
end
// Reduce the array
always_comb begin
automatic logic [31:0] readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<7; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
assign cpuif_rd_ack = readback_done;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
endmodule

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src/eth/regs/eth_mac_25g_us_regs_pkg.sv Normal file
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// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package eth_mac_25g_us_regs_pkg;
localparam ETH_MAC_25G_US_REGS_DATA_WIDTH = 32;
localparam ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH = 7;
localparam ETH_MAC_25G_US_REGS_SIZE = 'h60;
typedef struct {
logic next;
} eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__xcvr_gtpowergood_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__xcvr_gtpowergood_out__in_t xcvr_gtpowergood_out;
} eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__xcvr_qpll0lock_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__xcvr_qpll0lock_out__in_t xcvr_qpll0lock_out;
} eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__xcvr_qpll1lock_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__xcvr_qpll1lock_out__in_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__in_t;
typedef struct {
eth_mac_25g_us_regs__common__xcvr_gtpowergood_out__in_t xcvr_gtpowergood_out;
eth_mac_25g_us_regs__common__xcvr_qpll0lock_out__in_t xcvr_qpll0lock_out;
eth_mac_25g_us_regs__common__xcvr_qpll1lock_out__in_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__lane__rx_block_lock__rx_block_lock__in_t;
typedef struct {
eth_mac_25g_us_regs__lane__rx_block_lock__rx_block_lock__in_t rx_block_lock;
} eth_mac_25g_us_regs__lane__rx_block_lock__in_t;
typedef struct {
logic next;
} eth_mac_25g_us_regs__lane__rx_status__rx_status__in_t;
typedef struct {
eth_mac_25g_us_regs__lane__rx_status__rx_status__in_t rx_status;
} eth_mac_25g_us_regs__lane__rx_status__in_t;
typedef struct {
eth_mac_25g_us_regs__lane__rx_block_lock__in_t rx_block_lock;
eth_mac_25g_us_regs__lane__rx_status__in_t rx_status;
} eth_mac_25g_us_regs__lane__in_t;
typedef struct {
eth_mac_25g_us_regs__common__in_t common;
eth_mac_25g_us_regs__lane__in_t lanes[2];
} eth_mac_25g_us_regs__in_t;
endpackage

0
src/pcie_dma_wrapper.sv → src/pcie/pcie_dma_wrapper.sv
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2
src/pcie/regs/compile_regs.sh Executable file
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peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif apb4-flat

0
src/regs/pcie_dma_regs.rdl → src/pcie/regs/pcie_dma_regs.rdl
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0
src/regs/pcie_dma_regs.sv → src/pcie/regs/pcie_dma_regs.sv
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0
src/regs/pcie_dma_regs_pkg.sv → src/pcie/regs/pcie_dma_regs_pkg.sv
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6
src/pcie/regs/pcie_top_regs.rdl Normal file
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addrmap pcie_top_regs {
name = "";
desc = "";
external pcie_dma_regs pcie_dma_regs;
};

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src/pcie/regs/pcie_top_regs.sv Normal file
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//==========================================================
// Module: pcie_top_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module pcie_top_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [5:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_pcie_dma_regs_PCLK,
output logic m_apb_pcie_dma_regs_PRESETn,
output logic m_apb_pcie_dma_regs_PSEL,
output logic m_apb_pcie_dma_regs_PENABLE,
output logic m_apb_pcie_dma_regs_PWRITE,
output logic [5:0] m_apb_pcie_dma_regs_PADDR,
output logic [2:0] m_apb_pcie_dma_regs_PPROT,
output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
input logic [31:0] m_apb_pcie_dma_regs_PRDATA,
input logic m_apb_pcie_dma_regs_PREADY,
input logic m_apb_pcie_dma_regs_PSLVERR
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [5:0] cpuif_wr_addr;
logic [5:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic pcie_dma_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (6'h38))) begin
cpuif_wr_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (6'h38))) begin
cpuif_rd_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

18
src/pcie/regs/pcie_top_regs_pkg.sv Normal file
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@@ -0,0 +1,18 @@
//==========================================================
// Package: pcie_top_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package pcie_top_regs_pkg;
localparam PCIE_TOP_REGS_DATA_WIDTH = 32;
localparam PCIE_TOP_REGS_MIN_ADDR_WIDTH = 6;
localparam PCIE_TOP_REGS_SIZE = 'h38;
localparam PCIE_TOP_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
endpackage

0
src/regs/verilator.vlt → src/pcie/regs/verilator.vlt
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6
src/regs/alibaba_pcie_top.rdl Normal file
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@@ -0,0 +1,6 @@
addrmap alibaba_pcie_top_regs {
name = "Alibaba PCIe Top";
external pcie_top_regs pcie_top_regs;
external eth_dma_wrapper_regs eth_dma_wrapper_regs;
};

190
src/regs/alibaba_pcie_top_regs.h Normal file
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// Generated by PeakRDL-cheader - A free and open-source header generator
// https://github.com/SystemRDL/PeakRDL-cheader
#ifndef ALIBABA_PCIE_TOP_REGS_H
#define ALIBABA_PCIE_TOP_REGS_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <assert.h>
// Reg - pcie_dma_regs::dma_rd::src_addr_low
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_LOW__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_rd::src_addr_high
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_RD__SRC_ADDR_HIGH__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_rd::dst_addr
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bm 0xffff
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_bw 16
#define PCIE_DMA_REGS__DMA_RD__DST_ADDR__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_rd::length
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bm 0xffff
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bp 0
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_bw 16
#define PCIE_DMA_REGS__DMA_RD__LENGTH__LEN_reset 0x0
// Reg - pcie_dma_regs::dma_rd::trigger
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bm 0x1
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bp 0
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_bw 1
#define PCIE_DMA_REGS__DMA_RD__TRIGGER__TRIGGER_reset 0x0
// Reg - pcie_dma_regs::dma_rd::done
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bm 0x1
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bp 0
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_bw 1
#define PCIE_DMA_REGS__DMA_RD__DONE__DONE_reset 0x0
// Regfile - pcie_dma_regs::dma_rd
typedef struct __attribute__ ((__packed__)) {
uint32_t src_addr_low;
uint32_t src_addr_high;
uint32_t dst_addr;
uint32_t length;
uint32_t trigger;
uint32_t done;
} pcie_dma_regs__dma_rd_t;
// Reg - pcie_dma_regs::dma_wr::dst_addr_low
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_LOW__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_wr::dst_addr_high
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bm 0xffffffff
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_bw 32
#define PCIE_DMA_REGS__DMA_WR__DST_ADDR_HIGH__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_wr::src_addr
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bm 0xffff
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bp 0
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_bw 16
#define PCIE_DMA_REGS__DMA_WR__SRC_ADDR__ADDR_reset 0x0
// Reg - pcie_dma_regs::dma_wr::length
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bm 0xffff
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bp 0
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_bw 16
#define PCIE_DMA_REGS__DMA_WR__LENGTH__LEN_reset 0x0
// Reg - pcie_dma_regs::dma_wr::trigger
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bm 0x1
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bp 0
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_bw 1
#define PCIE_DMA_REGS__DMA_WR__TRIGGER__TRIGGER_reset 0x0
// Reg - pcie_dma_regs::dma_wr::done
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bm 0x1
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bp 0
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_bw 1
#define PCIE_DMA_REGS__DMA_WR__DONE__DONE_reset 0x0
// Regfile - pcie_dma_regs::dma_wr
typedef struct __attribute__ ((__packed__)) {
uint32_t dst_addr_low;
uint32_t dst_addr_high;
uint32_t src_addr;
uint32_t length;
uint32_t trigger;
uint32_t done;
} pcie_dma_regs__dma_wr_t;
// Addrmap - pcie_dma_regs
typedef struct __attribute__ ((__packed__)) {
pcie_dma_regs__dma_rd_t dma_rd;
uint8_t RESERVED_18_1f[0x8];
pcie_dma_regs__dma_wr_t dma_wr;
} pcie_dma_regs_t;
// Addrmap - pcie_top_regs
typedef struct __attribute__ ((__packed__)) {
pcie_dma_regs_t pcie_dma_regs;
} pcie_top_regs_t;
// Reg - eth_mac_25g_us_regs::common::xcvr_gtpowergood_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_GTPOWERGOOD_OUT__XCVR_GTPOWERGOOD_OUT_reset 0x0
// Reg - eth_mac_25g_us_regs::common::xcvr_qpll0lock_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL0LOCK_OUT__XCVR_QPLL0LOCK_OUT_reset 0x0
// Reg - eth_mac_25g_us_regs::common::xcvr_qpll1lock_out
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bm 0x1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bp 0
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_bw 1
#define ETH_MAC_25G_US_REGS__COMMON__XCVR_QPLL1LOCK_OUT__XCVR_QPLL1LOCK_OUT_reset 0x0
// Regfile - eth_mac_25g_us_regs::common
typedef struct __attribute__ ((__packed__)) {
uint32_t xcvr_gtpowergood_out;
uint32_t xcvr_qpll0lock_out;
uint32_t xcvr_qpll1lock_out;
} eth_mac_25g_us_regs__common_t;
// Reg - eth_mac_25g_us_regs::lane::rx_block_lock
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bm 0x1
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bp 0
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_bw 1
#define ETH_MAC_25G_US_REGS__LANE__RX_BLOCK_LOCK__RX_BLOCK_LOCK_reset 0x0
// Reg - eth_mac_25g_us_regs::lane::rx_status
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bm 0x1
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bp 0
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_bw 1
#define ETH_MAC_25G_US_REGS__LANE__RX_STATUS__RX_STATUS_reset 0x0
// Regfile - eth_mac_25g_us_regs::lane
typedef struct __attribute__ ((__packed__)) {
uint32_t rx_block_lock;
uint32_t rx_status;
uint8_t RESERVED_8_1f[0x18];
} eth_mac_25g_us_regs__lane__stride20_t;
// Addrmap - eth_mac_25g_us_regs
typedef struct __attribute__ ((__packed__)) {
eth_mac_25g_us_regs__common_t common;
uint8_t RESERVED_c_1f[0x14];
eth_mac_25g_us_regs__lane__stride20_t lanes[2];
} eth_mac_25g_us_regs_t;
// Addrmap - eth_dma_wrapper_regs
typedef struct __attribute__ ((__packed__)) {
eth_mac_25g_us_regs_t eth_mac_25g_us_regs;
uint8_t RESERVED_60_7f[0x20];
pcie_dma_regs_t pcie_dma_regs;
} eth_dma_wrapper_regs_t;
// Addrmap - alibaba_pcie_top_regs
typedef struct __attribute__ ((__packed__)) {
pcie_top_regs_t pcie_top_regs;
uint8_t RESERVED_38_ff[0xc8];
eth_dma_wrapper_regs_t eth_dma_wrapper_regs;
} alibaba_pcie_top_regs_t;
static_assert(sizeof(alibaba_pcie_top_regs_t) == 0x1b8, "Packing error");
#ifdef __cplusplus
}
#endif
#endif /* ALIBABA_PCIE_TOP_REGS_H */

185
src/regs/alibaba_pcie_top_regs.sv Normal file
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@@ -0,0 +1,185 @@
//==========================================================
// Module: alibaba_pcie_top_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module alibaba_pcie_top_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [8:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_pcie_top_regs_PCLK,
output logic m_apb_pcie_top_regs_PRESETn,
output logic m_apb_pcie_top_regs_PSEL,
output logic m_apb_pcie_top_regs_PENABLE,
output logic m_apb_pcie_top_regs_PWRITE,
output logic [5:0] m_apb_pcie_top_regs_PADDR,
output logic [2:0] m_apb_pcie_top_regs_PPROT,
output logic [31:0] m_apb_pcie_top_regs_PWDATA,
output logic [3:0] m_apb_pcie_top_regs_PSTRB,
input logic [31:0] m_apb_pcie_top_regs_PRDATA,
input logic m_apb_pcie_top_regs_PREADY,
input logic m_apb_pcie_top_regs_PSLVERR,
output logic m_apb_eth_dma_wrapper_regs_PCLK,
output logic m_apb_eth_dma_wrapper_regs_PRESETn,
output logic m_apb_eth_dma_wrapper_regs_PSEL,
output logic m_apb_eth_dma_wrapper_regs_PENABLE,
output logic m_apb_eth_dma_wrapper_regs_PWRITE,
output logic [7:0] m_apb_eth_dma_wrapper_regs_PADDR,
output logic [2:0] m_apb_eth_dma_wrapper_regs_PPROT,
output logic [31:0] m_apb_eth_dma_wrapper_regs_PWDATA,
output logic [3:0] m_apb_eth_dma_wrapper_regs_PSTRB,
input logic [31:0] m_apb_eth_dma_wrapper_regs_PRDATA,
input logic m_apb_eth_dma_wrapper_regs_PREADY,
input logic m_apb_eth_dma_wrapper_regs_PSLVERR
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [8:0] cpuif_wr_addr;
logic [8:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic pcie_top_regs;
logic eth_dma_wrapper_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_top_regs_PSEL = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
assign m_apb_pcie_top_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_top_regs_PWRITE = cpuif_wr_sel.pcie_top_regs;
assign m_apb_pcie_top_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_top_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_top_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_top_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_eth_dma_wrapper_regs_PSEL = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs_PENABLE = s_apb_PENABLE;
assign m_apb_eth_dma_wrapper_regs_PWRITE = cpuif_wr_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs_PADDR = s_apb_PADDR[7:0];
assign m_apb_eth_dma_wrapper_regs_PPROT = s_apb_PPROT;
assign m_apb_eth_dma_wrapper_regs_PWDATA = cpuif_wr_data;
assign m_apb_eth_dma_wrapper_regs_PSTRB = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
cpuif_rd_ack = m_apb_pcie_top_regs_PREADY;
cpuif_rd_err = m_apb_pcie_top_regs_PSLVERR;
end
if (cpuif_rd_sel.pcie_top_regs) begin
cpuif_rd_data = m_apb_pcie_top_regs_PRDATA;
end
if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
cpuif_rd_ack = m_apb_eth_dma_wrapper_regs_PREADY;
cpuif_rd_err = m_apb_eth_dma_wrapper_regs_PSLVERR;
end
if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
cpuif_rd_data = m_apb_eth_dma_wrapper_regs_PRDATA;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (9'h38))) begin
cpuif_wr_sel.pcie_top_regs = 1'b1;
end
else if ((cpuif_wr_addr >= (9'h100)) && (cpuif_wr_addr < (9'h1b8))) begin
cpuif_wr_sel.eth_dma_wrapper_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (9'h38))) begin
cpuif_rd_sel.pcie_top_regs = 1'b1;
end
else if ((cpuif_rd_addr >= (9'h100)) && (cpuif_rd_addr < (9'h1b8))) begin
cpuif_rd_sel.eth_dma_wrapper_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

19
src/regs/alibaba_pcie_top_regs_pkg.sv Normal file
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@@ -0,0 +1,19 @@
//==========================================================
// Package: alibaba_pcie_top_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package alibaba_pcie_top_regs_pkg;
localparam ALIBABA_PCIE_TOP_REGS_DATA_WIDTH = 32;
localparam ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH = 9;
localparam ALIBABA_PCIE_TOP_REGS_SIZE = 'h1b8;
localparam ALIBABA_PCIE_TOP_REGS_PCIE_TOP_REGS_ADDR_WIDTH = 6;
localparam ALIBABA_PCIE_TOP_REGS_ETH_DMA_WRAPPER_REGS_ADDR_WIDTH = 8;
endpackage

5
src/regs/compile_regs.sh
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@@ -1 +1,4 @@
peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif apb4-flat
peakrdl c-header -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.h

2
sub/taxi

Submodule sub/taxi updated: 2391e4f366...729bf79427