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This commit is contained in:
Byron Lathi
2025-11-22 12:30:57 -08:00
parent 0de33aaa1b
commit de33a46c78
27 changed files with 1363 additions and 177 deletions
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2
src/pcie/regs/compile_regs.sh Executable file
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peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif apb4-flat

172
src/pcie/regs/pcie_dma_regs.rdl Normal file
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addrmap pcie_dma_regs {
name = "PCIe DMA Regs";
desc = "";
regfile {
reg {
name = "DMA Read Source Address Low";
desc = "Address which will be read over PCIe (System Address)";
field {
name = "addr";
desc = "";
hw = r;
sw = rw;
} addr[31:0] = 0x0;
} src_addr_low @ 0x0;
reg {
name = "DMA Read Source Address High";
desc = "Address which will be read over PCIe (System Address)";
field {
name = "addr";
desc = "";
hw = r;
sw = rw;
} addr[31:0] = 0x0;
} src_addr_high @ 0x4;
reg {
name = "DMA Read Dest Address";
desc = "Address where data will be written on chip (Local Address)";
field {
name = "addr";
desc = "";
hw = r;
sw = rw;
} addr[15:0] = 0x0;
} dst_addr @ 0x8;
reg {
name = "Length";
desc = "";
field {
name = "Length";
desc = "";
hw = r;
sw = rw;
} len[15:0] = 0x0;
} length @ 0xc;
reg {
name = "Trigger";
desc = "Trigger DMA";
field {
name = "Trigger";
desc = "";
hwclr;
hw = r;
sw = w;
} trigger[0:0] = 0x0;
} trigger @ 0x10;
reg {
name = "Done";
desc = "DMA is done";
field {
name = "Done";
desc = "";
hwset;
rclr;
hw = r;
sw = r;
} done[0:0] = 0x0;
} done @ 0x14;
} dma_rd @ 0x0;
regfile {
reg {
name = "DMA Read Dest Address Low";
desc = "Address which will be written to over PCIe (System Address)";
field {
name = "addr";
desc = "";
hw = r;
sw = rw;
} addr[31:0] = 0x0;
} dst_addr_low @ 0x0;
reg {
name = "DMA Read Dest Address High";
desc = "Address which will be written to over PCIe (System Address)";
field {
name = "addr";
desc = "";
hw = r;
sw = rw;
} addr[31:0] = 0x0;
} dst_addr_high @ 0x4;
reg {
name = "DMA Read Source Address";
desc = "Address where data will be read from on chip (Local Address)";
field {
name = "addr";
desc = "";
hw = r;
sw = rw;
} addr[15:0] = 0x0;
} src_addr @ 0x8;
reg {
name = "Length";
desc = "";
field {
name = "Length";
desc = "";
hw = r;
sw = rw;
} len[15:0] = 0x0;
} length @ 0xc;
reg {
name = "Trigger";
desc = "Trigger DMA";
field {
name = "Trigger";
desc = "";
hwclr;
hw = r;
sw = w;
} trigger[0:0] = 0x0;
} trigger @ 0x10;
reg {
name = "Done";
desc = "DMA is done";
field {
name = "Done";
desc = "";
hwset;
rclr;
hw = r;
sw = r;
} done[0:0] = 0x0;
} done @ 0x14;
} dma_wr @ 0x20;
};

627
src/pcie/regs/pcie_dma_regs.sv Normal file
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// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
module pcie_dma_regs (
input wire clk,
input wire rst,
input wire s_apb_psel,
input wire s_apb_penable,
input wire s_apb_pwrite,
input wire [2:0] s_apb_pprot,
input wire [5:0] s_apb_paddr,
input wire [31:0] s_apb_pwdata,
input wire [3:0] s_apb_pstrb,
output logic s_apb_pready,
output logic [31:0] s_apb_prdata,
output logic s_apb_pslverr,
input pcie_dma_regs_pkg::pcie_dma_regs__in_t hwif_in,
output pcie_dma_regs_pkg::pcie_dma_regs__out_t hwif_out
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_req_is_wr;
logic [5:0] cpuif_addr;
logic [31:0] cpuif_wr_data;
logic [31:0] cpuif_wr_biten;
logic cpuif_req_stall_wr;
logic cpuif_req_stall_rd;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
logic cpuif_wr_ack;
logic cpuif_wr_err;
// Request
logic is_active;
always_ff @(posedge clk) begin
if(rst) begin
is_active <= '0;
cpuif_req <= '0;
cpuif_req_is_wr <= '0;
cpuif_addr <= '0;
cpuif_wr_data <= '0;
cpuif_wr_biten <= '0;
end else begin
if(~is_active) begin
if(s_apb_psel) begin
is_active <= '1;
cpuif_req <= '1;
cpuif_req_is_wr <= s_apb_pwrite;
cpuif_addr <= {s_apb_paddr[5:2], 2'b0};
cpuif_wr_data <= s_apb_pwdata;
for(int i=0; i<4; i++) begin
cpuif_wr_biten[i*8 +: 8] <= {8{s_apb_pstrb[i]}};
end
end
end else begin
cpuif_req <= '0;
if(cpuif_rd_ack || cpuif_wr_ack) begin
is_active <= '0;
end
end
end
end
// Response
assign s_apb_pready = cpuif_rd_ack | cpuif_wr_ack;
assign s_apb_prdata = cpuif_rd_data;
assign s_apb_pslverr = cpuif_rd_err | cpuif_wr_err;
logic cpuif_req_masked;
// Read & write latencies are balanced. Stalls not required
assign cpuif_req_stall_rd = '0;
assign cpuif_req_stall_wr = '0;
assign cpuif_req_masked = cpuif_req
& !(!cpuif_req_is_wr & cpuif_req_stall_rd)
& !(cpuif_req_is_wr & cpuif_req_stall_wr);
//--------------------------------------------------------------------------
// Address Decode
//--------------------------------------------------------------------------
typedef struct {
struct {
logic src_addr_low;
logic src_addr_high;
logic dst_addr;
logic length;
logic trigger;
logic done;
} dma_rd;
struct {
logic dst_addr_low;
logic dst_addr_high;
logic src_addr;
logic length;
logic trigger;
logic done;
} dma_wr;
} decoded_reg_strb_t;
decoded_reg_strb_t decoded_reg_strb;
logic decoded_err;
logic decoded_req;
logic decoded_req_is_wr;
logic [31:0] decoded_wr_data;
logic [31:0] decoded_wr_biten;
always_comb begin
automatic logic is_valid_addr;
automatic logic is_invalid_rw;
is_valid_addr = '1; // No error checking on valid address access
is_invalid_rw = '0;
decoded_reg_strb.dma_rd.src_addr_low = cpuif_req_masked & (cpuif_addr == 6'h0);
decoded_reg_strb.dma_rd.src_addr_high = cpuif_req_masked & (cpuif_addr == 6'h4);
decoded_reg_strb.dma_rd.dst_addr = cpuif_req_masked & (cpuif_addr == 6'h8);
decoded_reg_strb.dma_rd.length = cpuif_req_masked & (cpuif_addr == 6'hc);
decoded_reg_strb.dma_rd.trigger = cpuif_req_masked & (cpuif_addr == 6'h10) & cpuif_req_is_wr;
decoded_reg_strb.dma_rd.done = cpuif_req_masked & (cpuif_addr == 6'h14) & !cpuif_req_is_wr;
decoded_reg_strb.dma_wr.dst_addr_low = cpuif_req_masked & (cpuif_addr == 6'h20);
decoded_reg_strb.dma_wr.dst_addr_high = cpuif_req_masked & (cpuif_addr == 6'h24);
decoded_reg_strb.dma_wr.src_addr = cpuif_req_masked & (cpuif_addr == 6'h28);
decoded_reg_strb.dma_wr.length = cpuif_req_masked & (cpuif_addr == 6'h2c);
decoded_reg_strb.dma_wr.trigger = cpuif_req_masked & (cpuif_addr == 6'h30) & cpuif_req_is_wr;
decoded_reg_strb.dma_wr.done = cpuif_req_masked & (cpuif_addr == 6'h34) & !cpuif_req_is_wr;
decoded_err = (~is_valid_addr | is_invalid_rw) & decoded_req;
end
// Pass down signals to next stage
assign decoded_req = cpuif_req_masked;
assign decoded_req_is_wr = cpuif_req_is_wr;
assign decoded_wr_data = cpuif_wr_data;
assign decoded_wr_biten = cpuif_wr_biten;
//--------------------------------------------------------------------------
// Field logic
//--------------------------------------------------------------------------
typedef struct {
struct {
struct {
struct {
logic [31:0] next;
logic load_next;
} addr;
} src_addr_low;
struct {
struct {
logic [31:0] next;
logic load_next;
} addr;
} src_addr_high;
struct {
struct {
logic [15:0] next;
logic load_next;
} addr;
} dst_addr;
struct {
struct {
logic [15:0] next;
logic load_next;
} len;
} length;
struct {
struct {
logic next;
logic load_next;
} trigger;
} trigger;
struct {
struct {
logic next;
logic load_next;
} done;
} done;
} dma_rd;
struct {
struct {
struct {
logic [31:0] next;
logic load_next;
} addr;
} dst_addr_low;
struct {
struct {
logic [31:0] next;
logic load_next;
} addr;
} dst_addr_high;
struct {
struct {
logic [15:0] next;
logic load_next;
} addr;
} src_addr;
struct {
struct {
logic [15:0] next;
logic load_next;
} len;
} length;
struct {
struct {
logic next;
logic load_next;
} trigger;
} trigger;
struct {
struct {
logic next;
logic load_next;
} done;
} done;
} dma_wr;
} field_combo_t;
field_combo_t field_combo;
typedef struct {
struct {
struct {
struct {
logic [31:0] value;
} addr;
} src_addr_low;
struct {
struct {
logic [31:0] value;
} addr;
} src_addr_high;
struct {
struct {
logic [15:0] value;
} addr;
} dst_addr;
struct {
struct {
logic [15:0] value;
} len;
} length;
struct {
struct {
logic value;
} trigger;
} trigger;
struct {
struct {
logic value;
} done;
} done;
} dma_rd;
struct {
struct {
struct {
logic [31:0] value;
} addr;
} dst_addr_low;
struct {
struct {
logic [31:0] value;
} addr;
} dst_addr_high;
struct {
struct {
logic [15:0] value;
} addr;
} src_addr;
struct {
struct {
logic [15:0] value;
} len;
} length;
struct {
struct {
logic value;
} trigger;
} trigger;
struct {
struct {
logic value;
} done;
} done;
} dma_wr;
} field_storage_t;
field_storage_t field_storage;
// Field: pcie_dma_regs.dma_rd.src_addr_low.addr
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_rd.src_addr_low.addr.value;
load_next_c = '0;
if(decoded_reg_strb.dma_rd.src_addr_low && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_rd.src_addr_low.addr.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.dma_rd.src_addr_low.addr.next = next_c;
field_combo.dma_rd.src_addr_low.addr.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_rd.src_addr_low.addr.value <= 32'h0;
end else begin
if(field_combo.dma_rd.src_addr_low.addr.load_next) begin
field_storage.dma_rd.src_addr_low.addr.value <= field_combo.dma_rd.src_addr_low.addr.next;
end
end
end
assign hwif_out.dma_rd.src_addr_low.addr.value = field_storage.dma_rd.src_addr_low.addr.value;
// Field: pcie_dma_regs.dma_rd.src_addr_high.addr
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_rd.src_addr_high.addr.value;
load_next_c = '0;
if(decoded_reg_strb.dma_rd.src_addr_high && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_rd.src_addr_high.addr.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.dma_rd.src_addr_high.addr.next = next_c;
field_combo.dma_rd.src_addr_high.addr.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_rd.src_addr_high.addr.value <= 32'h0;
end else begin
if(field_combo.dma_rd.src_addr_high.addr.load_next) begin
field_storage.dma_rd.src_addr_high.addr.value <= field_combo.dma_rd.src_addr_high.addr.next;
end
end
end
assign hwif_out.dma_rd.src_addr_high.addr.value = field_storage.dma_rd.src_addr_high.addr.value;
// Field: pcie_dma_regs.dma_rd.dst_addr.addr
always_comb begin
automatic logic [15:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_rd.dst_addr.addr.value;
load_next_c = '0;
if(decoded_reg_strb.dma_rd.dst_addr && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_rd.dst_addr.addr.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
load_next_c = '1;
end
field_combo.dma_rd.dst_addr.addr.next = next_c;
field_combo.dma_rd.dst_addr.addr.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_rd.dst_addr.addr.value <= 16'h0;
end else begin
if(field_combo.dma_rd.dst_addr.addr.load_next) begin
field_storage.dma_rd.dst_addr.addr.value <= field_combo.dma_rd.dst_addr.addr.next;
end
end
end
assign hwif_out.dma_rd.dst_addr.addr.value = field_storage.dma_rd.dst_addr.addr.value;
// Field: pcie_dma_regs.dma_rd.length.len
always_comb begin
automatic logic [15:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_rd.length.len.value;
load_next_c = '0;
if(decoded_reg_strb.dma_rd.length && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_rd.length.len.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
load_next_c = '1;
end
field_combo.dma_rd.length.len.next = next_c;
field_combo.dma_rd.length.len.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_rd.length.len.value <= 16'h0;
end else begin
if(field_combo.dma_rd.length.len.load_next) begin
field_storage.dma_rd.length.len.value <= field_combo.dma_rd.length.len.next;
end
end
end
assign hwif_out.dma_rd.length.len.value = field_storage.dma_rd.length.len.value;
// Field: pcie_dma_regs.dma_rd.trigger.trigger
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_rd.trigger.trigger.value;
load_next_c = '0;
if(decoded_reg_strb.dma_rd.trigger && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_rd.trigger.trigger.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
end else if(hwif_in.dma_rd.trigger.trigger.hwclr) begin // HW Clear
next_c = '0;
load_next_c = '1;
end
field_combo.dma_rd.trigger.trigger.next = next_c;
field_combo.dma_rd.trigger.trigger.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_rd.trigger.trigger.value <= 1'h0;
end else begin
if(field_combo.dma_rd.trigger.trigger.load_next) begin
field_storage.dma_rd.trigger.trigger.value <= field_combo.dma_rd.trigger.trigger.next;
end
end
end
assign hwif_out.dma_rd.trigger.trigger.value = field_storage.dma_rd.trigger.trigger.value;
// Field: pcie_dma_regs.dma_rd.done.done
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_rd.done.done.value;
load_next_c = '0;
if(decoded_reg_strb.dma_rd.done && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.dma_rd.done.done.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.dma_rd.done.done.next = next_c;
field_combo.dma_rd.done.done.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_rd.done.done.value <= 1'h0;
end else begin
if(field_combo.dma_rd.done.done.load_next) begin
field_storage.dma_rd.done.done.value <= field_combo.dma_rd.done.done.next;
end
end
end
assign hwif_out.dma_rd.done.done.value = field_storage.dma_rd.done.done.value;
// Field: pcie_dma_regs.dma_wr.dst_addr_low.addr
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_wr.dst_addr_low.addr.value;
load_next_c = '0;
if(decoded_reg_strb.dma_wr.dst_addr_low && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_wr.dst_addr_low.addr.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.dma_wr.dst_addr_low.addr.next = next_c;
field_combo.dma_wr.dst_addr_low.addr.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_wr.dst_addr_low.addr.value <= 32'h0;
end else begin
if(field_combo.dma_wr.dst_addr_low.addr.load_next) begin
field_storage.dma_wr.dst_addr_low.addr.value <= field_combo.dma_wr.dst_addr_low.addr.next;
end
end
end
assign hwif_out.dma_wr.dst_addr_low.addr.value = field_storage.dma_wr.dst_addr_low.addr.value;
// Field: pcie_dma_regs.dma_wr.dst_addr_high.addr
always_comb begin
automatic logic [31:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_wr.dst_addr_high.addr.value;
load_next_c = '0;
if(decoded_reg_strb.dma_wr.dst_addr_high && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_wr.dst_addr_high.addr.value & ~decoded_wr_biten[31:0]) | (decoded_wr_data[31:0] & decoded_wr_biten[31:0]);
load_next_c = '1;
end
field_combo.dma_wr.dst_addr_high.addr.next = next_c;
field_combo.dma_wr.dst_addr_high.addr.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_wr.dst_addr_high.addr.value <= 32'h0;
end else begin
if(field_combo.dma_wr.dst_addr_high.addr.load_next) begin
field_storage.dma_wr.dst_addr_high.addr.value <= field_combo.dma_wr.dst_addr_high.addr.next;
end
end
end
assign hwif_out.dma_wr.dst_addr_high.addr.value = field_storage.dma_wr.dst_addr_high.addr.value;
// Field: pcie_dma_regs.dma_wr.src_addr.addr
always_comb begin
automatic logic [15:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_wr.src_addr.addr.value;
load_next_c = '0;
if(decoded_reg_strb.dma_wr.src_addr && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_wr.src_addr.addr.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
load_next_c = '1;
end
field_combo.dma_wr.src_addr.addr.next = next_c;
field_combo.dma_wr.src_addr.addr.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_wr.src_addr.addr.value <= 16'h0;
end else begin
if(field_combo.dma_wr.src_addr.addr.load_next) begin
field_storage.dma_wr.src_addr.addr.value <= field_combo.dma_wr.src_addr.addr.next;
end
end
end
assign hwif_out.dma_wr.src_addr.addr.value = field_storage.dma_wr.src_addr.addr.value;
// Field: pcie_dma_regs.dma_wr.length.len
always_comb begin
automatic logic [15:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_wr.length.len.value;
load_next_c = '0;
if(decoded_reg_strb.dma_wr.length && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_wr.length.len.value & ~decoded_wr_biten[15:0]) | (decoded_wr_data[15:0] & decoded_wr_biten[15:0]);
load_next_c = '1;
end
field_combo.dma_wr.length.len.next = next_c;
field_combo.dma_wr.length.len.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_wr.length.len.value <= 16'h0;
end else begin
if(field_combo.dma_wr.length.len.load_next) begin
field_storage.dma_wr.length.len.value <= field_combo.dma_wr.length.len.next;
end
end
end
assign hwif_out.dma_wr.length.len.value = field_storage.dma_wr.length.len.value;
// Field: pcie_dma_regs.dma_wr.trigger.trigger
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_wr.trigger.trigger.value;
load_next_c = '0;
if(decoded_reg_strb.dma_wr.trigger && decoded_req_is_wr) begin // SW write
next_c = (field_storage.dma_wr.trigger.trigger.value & ~decoded_wr_biten[0:0]) | (decoded_wr_data[0:0] & decoded_wr_biten[0:0]);
load_next_c = '1;
end else if(hwif_in.dma_wr.trigger.trigger.hwclr) begin // HW Clear
next_c = '0;
load_next_c = '1;
end
field_combo.dma_wr.trigger.trigger.next = next_c;
field_combo.dma_wr.trigger.trigger.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_wr.trigger.trigger.value <= 1'h0;
end else begin
if(field_combo.dma_wr.trigger.trigger.load_next) begin
field_storage.dma_wr.trigger.trigger.value <= field_combo.dma_wr.trigger.trigger.next;
end
end
end
assign hwif_out.dma_wr.trigger.trigger.value = field_storage.dma_wr.trigger.trigger.value;
// Field: pcie_dma_regs.dma_wr.done.done
always_comb begin
automatic logic [0:0] next_c;
automatic logic load_next_c;
next_c = field_storage.dma_wr.done.done.value;
load_next_c = '0;
if(decoded_reg_strb.dma_wr.done && !decoded_req_is_wr) begin // SW clear on read
next_c = '0;
load_next_c = '1;
end else if(hwif_in.dma_wr.done.done.hwset) begin // HW Set
next_c = '1;
load_next_c = '1;
end
field_combo.dma_wr.done.done.next = next_c;
field_combo.dma_wr.done.done.load_next = load_next_c;
end
always_ff @(posedge clk) begin
if(rst) begin
field_storage.dma_wr.done.done.value <= 1'h0;
end else begin
if(field_combo.dma_wr.done.done.load_next) begin
field_storage.dma_wr.done.done.value <= field_combo.dma_wr.done.done.next;
end
end
end
assign hwif_out.dma_wr.done.done.value = field_storage.dma_wr.done.done.value;
//--------------------------------------------------------------------------
// Write response
//--------------------------------------------------------------------------
assign cpuif_wr_ack = decoded_req & decoded_req_is_wr;
// Writes are always granted with no error response
assign cpuif_wr_err = '0;
//--------------------------------------------------------------------------
// Readback
//--------------------------------------------------------------------------
logic readback_err;
logic readback_done;
logic [31:0] readback_data;
// Assign readback values to a flattened array
logic [31:0] readback_array[10];
assign readback_array[0][31:0] = (decoded_reg_strb.dma_rd.src_addr_low && !decoded_req_is_wr) ? field_storage.dma_rd.src_addr_low.addr.value : '0;
assign readback_array[1][31:0] = (decoded_reg_strb.dma_rd.src_addr_high && !decoded_req_is_wr) ? field_storage.dma_rd.src_addr_high.addr.value : '0;
assign readback_array[2][15:0] = (decoded_reg_strb.dma_rd.dst_addr && !decoded_req_is_wr) ? field_storage.dma_rd.dst_addr.addr.value : '0;
assign readback_array[2][31:16] = '0;
assign readback_array[3][15:0] = (decoded_reg_strb.dma_rd.length && !decoded_req_is_wr) ? field_storage.dma_rd.length.len.value : '0;
assign readback_array[3][31:16] = '0;
assign readback_array[4][0:0] = (decoded_reg_strb.dma_rd.done && !decoded_req_is_wr) ? field_storage.dma_rd.done.done.value : '0;
assign readback_array[4][31:1] = '0;
assign readback_array[5][31:0] = (decoded_reg_strb.dma_wr.dst_addr_low && !decoded_req_is_wr) ? field_storage.dma_wr.dst_addr_low.addr.value : '0;
assign readback_array[6][31:0] = (decoded_reg_strb.dma_wr.dst_addr_high && !decoded_req_is_wr) ? field_storage.dma_wr.dst_addr_high.addr.value : '0;
assign readback_array[7][15:0] = (decoded_reg_strb.dma_wr.src_addr && !decoded_req_is_wr) ? field_storage.dma_wr.src_addr.addr.value : '0;
assign readback_array[7][31:16] = '0;
assign readback_array[8][15:0] = (decoded_reg_strb.dma_wr.length && !decoded_req_is_wr) ? field_storage.dma_wr.length.len.value : '0;
assign readback_array[8][31:16] = '0;
assign readback_array[9][0:0] = (decoded_reg_strb.dma_wr.done && !decoded_req_is_wr) ? field_storage.dma_wr.done.done.value : '0;
assign readback_array[9][31:1] = '0;
// Reduce the array
always_comb begin
automatic logic [31:0] readback_data_var;
readback_done = decoded_req & ~decoded_req_is_wr;
readback_err = '0;
readback_data_var = '0;
for(int i=0; i<10; i++) readback_data_var |= readback_array[i];
readback_data = readback_data_var;
end
assign cpuif_rd_ack = readback_done;
assign cpuif_rd_data = readback_data;
assign cpuif_rd_err = readback_err;
endmodule

175
src/pcie/regs/pcie_dma_regs_pkg.sv Normal file
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// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
// https://github.com/SystemRDL/PeakRDL-regblock
package pcie_dma_regs_pkg;
localparam PCIE_DMA_REGS_DATA_WIDTH = 32;
localparam PCIE_DMA_REGS_MIN_ADDR_WIDTH = 6;
localparam PCIE_DMA_REGS_SIZE = 'h38;
typedef struct {
logic hwclr;
} pcie_dma_regs__dma_rd__trigger__trigger__in_t;
typedef struct {
pcie_dma_regs__dma_rd__trigger__trigger__in_t trigger;
} pcie_dma_regs__dma_rd__trigger__in_t;
typedef struct {
logic hwset;
} pcie_dma_regs__dma_rd__done__done__in_t;
typedef struct {
pcie_dma_regs__dma_rd__done__done__in_t done;
} pcie_dma_regs__dma_rd__done__in_t;
typedef struct {
pcie_dma_regs__dma_rd__trigger__in_t trigger;
pcie_dma_regs__dma_rd__done__in_t done;
} pcie_dma_regs__dma_rd__in_t;
typedef struct {
logic hwclr;
} pcie_dma_regs__dma_wr__trigger__trigger__in_t;
typedef struct {
pcie_dma_regs__dma_wr__trigger__trigger__in_t trigger;
} pcie_dma_regs__dma_wr__trigger__in_t;
typedef struct {
logic hwset;
} pcie_dma_regs__dma_wr__done__done__in_t;
typedef struct {
pcie_dma_regs__dma_wr__done__done__in_t done;
} pcie_dma_regs__dma_wr__done__in_t;
typedef struct {
pcie_dma_regs__dma_wr__trigger__in_t trigger;
pcie_dma_regs__dma_wr__done__in_t done;
} pcie_dma_regs__dma_wr__in_t;
typedef struct {
pcie_dma_regs__dma_rd__in_t dma_rd;
pcie_dma_regs__dma_wr__in_t dma_wr;
} pcie_dma_regs__in_t;
typedef struct {
logic [31:0] value;
} pcie_dma_regs__dma_rd__src_addr_low__addr__out_t;
typedef struct {
pcie_dma_regs__dma_rd__src_addr_low__addr__out_t addr;
} pcie_dma_regs__dma_rd__src_addr_low__out_t;
typedef struct {
logic [31:0] value;
} pcie_dma_regs__dma_rd__src_addr_high__addr__out_t;
typedef struct {
pcie_dma_regs__dma_rd__src_addr_high__addr__out_t addr;
} pcie_dma_regs__dma_rd__src_addr_high__out_t;
typedef struct {
logic [15:0] value;
} pcie_dma_regs__dma_rd__dst_addr__addr__out_t;
typedef struct {
pcie_dma_regs__dma_rd__dst_addr__addr__out_t addr;
} pcie_dma_regs__dma_rd__dst_addr__out_t;
typedef struct {
logic [15:0] value;
} pcie_dma_regs__dma_rd__length__len__out_t;
typedef struct {
pcie_dma_regs__dma_rd__length__len__out_t len;
} pcie_dma_regs__dma_rd__length__out_t;
typedef struct {
logic value;
} pcie_dma_regs__dma_rd__trigger__trigger__out_t;
typedef struct {
pcie_dma_regs__dma_rd__trigger__trigger__out_t trigger;
} pcie_dma_regs__dma_rd__trigger__out_t;
typedef struct {
logic value;
} pcie_dma_regs__dma_rd__done__done__out_t;
typedef struct {
pcie_dma_regs__dma_rd__done__done__out_t done;
} pcie_dma_regs__dma_rd__done__out_t;
typedef struct {
pcie_dma_regs__dma_rd__src_addr_low__out_t src_addr_low;
pcie_dma_regs__dma_rd__src_addr_high__out_t src_addr_high;
pcie_dma_regs__dma_rd__dst_addr__out_t dst_addr;
pcie_dma_regs__dma_rd__length__out_t length;
pcie_dma_regs__dma_rd__trigger__out_t trigger;
pcie_dma_regs__dma_rd__done__out_t done;
} pcie_dma_regs__dma_rd__out_t;
typedef struct {
logic [31:0] value;
} pcie_dma_regs__dma_wr__dst_addr_low__addr__out_t;
typedef struct {
pcie_dma_regs__dma_wr__dst_addr_low__addr__out_t addr;
} pcie_dma_regs__dma_wr__dst_addr_low__out_t;
typedef struct {
logic [31:0] value;
} pcie_dma_regs__dma_wr__dst_addr_high__addr__out_t;
typedef struct {
pcie_dma_regs__dma_wr__dst_addr_high__addr__out_t addr;
} pcie_dma_regs__dma_wr__dst_addr_high__out_t;
typedef struct {
logic [15:0] value;
} pcie_dma_regs__dma_wr__src_addr__addr__out_t;
typedef struct {
pcie_dma_regs__dma_wr__src_addr__addr__out_t addr;
} pcie_dma_regs__dma_wr__src_addr__out_t;
typedef struct {
logic [15:0] value;
} pcie_dma_regs__dma_wr__length__len__out_t;
typedef struct {
pcie_dma_regs__dma_wr__length__len__out_t len;
} pcie_dma_regs__dma_wr__length__out_t;
typedef struct {
logic value;
} pcie_dma_regs__dma_wr__trigger__trigger__out_t;
typedef struct {
pcie_dma_regs__dma_wr__trigger__trigger__out_t trigger;
} pcie_dma_regs__dma_wr__trigger__out_t;
typedef struct {
logic value;
} pcie_dma_regs__dma_wr__done__done__out_t;
typedef struct {
pcie_dma_regs__dma_wr__done__done__out_t done;
} pcie_dma_regs__dma_wr__done__out_t;
typedef struct {
pcie_dma_regs__dma_wr__dst_addr_low__out_t dst_addr_low;
pcie_dma_regs__dma_wr__dst_addr_high__out_t dst_addr_high;
pcie_dma_regs__dma_wr__src_addr__out_t src_addr;
pcie_dma_regs__dma_wr__length__out_t length;
pcie_dma_regs__dma_wr__trigger__out_t trigger;
pcie_dma_regs__dma_wr__done__out_t done;
} pcie_dma_regs__dma_wr__out_t;
typedef struct {
pcie_dma_regs__dma_rd__out_t dma_rd;
pcie_dma_regs__dma_wr__out_t dma_wr;
} pcie_dma_regs__out_t;
endpackage

6
src/pcie/regs/pcie_top_regs.rdl Normal file
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addrmap pcie_top_regs {
name = "";
desc = "";
external pcie_dma_regs pcie_dma_regs;
};

152
src/pcie/regs/pcie_top_regs.sv Normal file
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//==========================================================
// Module: pcie_top_regs
// Description: CPU Interface Bus Decoder
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
module pcie_top_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [5:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_pcie_dma_regs_PCLK,
output logic m_apb_pcie_dma_regs_PRESETn,
output logic m_apb_pcie_dma_regs_PSEL,
output logic m_apb_pcie_dma_regs_PENABLE,
output logic m_apb_pcie_dma_regs_PWRITE,
output logic [5:0] m_apb_pcie_dma_regs_PADDR,
output logic [2:0] m_apb_pcie_dma_regs_PPROT,
output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
input logic [31:0] m_apb_pcie_dma_regs_PRDATA,
input logic m_apb_pcie_dma_regs_PREADY,
input logic m_apb_pcie_dma_regs_PSLVERR
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
//--------------------------------------------------------------------------
logic cpuif_req;
logic cpuif_wr_en;
logic cpuif_rd_en;
logic [5:0] cpuif_wr_addr;
logic [5:0] cpuif_rd_addr;
logic cpuif_wr_ack;
logic cpuif_wr_err;
logic [31:0] cpuif_wr_data;
logic [3:0] cpuif_wr_byte_en;
logic cpuif_rd_ack;
logic cpuif_rd_err;
logic [31:0] cpuif_rd_data;
//--------------------------------------------------------------------------
// Child instance signals
//--------------------------------------------------------------------------
typedef struct {
logic pcie_dma_regs;
logic cpuif_err;
} cpuif_sel_t;
cpuif_sel_t cpuif_wr_sel;
cpuif_sel_t cpuif_rd_sel;
//--------------------------------------------------------------------------
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
//--------------------------------------------------------------------------
always_comb begin
cpuif_rd_ack = '0;
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
end
end
//--------------------------------------------------------------------------
// Write Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all write select signals to 0
cpuif_wr_sel = '{default: '0};
if (cpuif_req && cpuif_wr_en) begin
// A write request is pending
if ((cpuif_wr_addr < (6'h38))) begin
cpuif_wr_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_wr_sel.cpuif_err = 1'b1;
end
end else begin
// No write request, all select signals remain 0
end
end
//--------------------------------------------------------------------------
// Read Address Decoder
//--------------------------------------------------------------------------
always_comb begin
// Default all read select signals to 0
cpuif_rd_sel = '{default: '0};
if (cpuif_req && cpuif_rd_en) begin
// A read request is pending
if ((cpuif_rd_addr < (6'h38))) begin
cpuif_rd_sel.pcie_dma_regs = 1'b1;
end
else begin
cpuif_rd_sel.cpuif_err = 1'b1;
end
end else begin
// No read request, all select signals remain 0
end
end
endmodule

18
src/pcie/regs/pcie_top_regs_pkg.sv Normal file
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//==========================================================
// Package: pcie_top_regs_pkg
// Description: CPU Interface Bus Decoder Package
// Author: PeakRDL-BusDecoder
// License: LGPL-3.0
// Date: 2025-11-22
// Version: 0.5.0
// Links:
// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
//==========================================================
package pcie_top_regs_pkg;
localparam PCIE_TOP_REGS_DATA_WIDTH = 32;
localparam PCIE_TOP_REGS_MIN_ADDR_WIDTH = 6;
localparam PCIE_TOP_REGS_SIZE = 'h38;
localparam PCIE_TOP_REGS_PCIE_DMA_REGS_ADDR_WIDTH = 6;
endpackage

4
src/pcie/regs/verilator.vlt Normal file
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`verilator_config
lint_off -rule MULTIDRIVEN -file "**/regs/*"
lint_off -file "**/regs/*"