reorg
This commit is contained in:
Byron Lathi
185
src/regs/alibaba_pcie_top_regs.sv
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185
src/regs/alibaba_pcie_top_regs.sv
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//==========================================================
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// Module: alibaba_pcie_top_regs
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// Description: CPU Interface Bus Decoder
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// Author: PeakRDL-BusDecoder
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// License: LGPL-3.0
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// Date: 2025-11-22
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// Version: 0.5.0
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// Links:
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// - https://github.com/arnavsacheti/PeakRDL-BusDecoder
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//==========================================================
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module alibaba_pcie_top_regs (
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input logic s_apb_PCLK,
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input logic s_apb_PRESETn,
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input logic s_apb_PSEL,
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input logic s_apb_PENABLE,
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input logic s_apb_PWRITE,
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input logic [8:0] s_apb_PADDR,
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input logic [2:0] s_apb_PPROT,
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input logic [31:0] s_apb_PWDATA,
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input logic [3:0] s_apb_PSTRB,
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output logic [31:0] s_apb_PRDATA,
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output logic s_apb_PREADY,
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output logic s_apb_PSLVERR,
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output logic m_apb_pcie_top_regs_PCLK,
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output logic m_apb_pcie_top_regs_PRESETn,
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output logic m_apb_pcie_top_regs_PSEL,
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output logic m_apb_pcie_top_regs_PENABLE,
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output logic m_apb_pcie_top_regs_PWRITE,
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output logic [5:0] m_apb_pcie_top_regs_PADDR,
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output logic [2:0] m_apb_pcie_top_regs_PPROT,
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output logic [31:0] m_apb_pcie_top_regs_PWDATA,
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output logic [3:0] m_apb_pcie_top_regs_PSTRB,
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input logic [31:0] m_apb_pcie_top_regs_PRDATA,
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input logic m_apb_pcie_top_regs_PREADY,
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input logic m_apb_pcie_top_regs_PSLVERR,
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output logic m_apb_eth_dma_wrapper_regs_PCLK,
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output logic m_apb_eth_dma_wrapper_regs_PRESETn,
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output logic m_apb_eth_dma_wrapper_regs_PSEL,
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output logic m_apb_eth_dma_wrapper_regs_PENABLE,
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output logic m_apb_eth_dma_wrapper_regs_PWRITE,
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output logic [7:0] m_apb_eth_dma_wrapper_regs_PADDR,
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output logic [2:0] m_apb_eth_dma_wrapper_regs_PPROT,
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output logic [31:0] m_apb_eth_dma_wrapper_regs_PWDATA,
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output logic [3:0] m_apb_eth_dma_wrapper_regs_PSTRB,
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input logic [31:0] m_apb_eth_dma_wrapper_regs_PRDATA,
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input logic m_apb_eth_dma_wrapper_regs_PREADY,
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input logic m_apb_eth_dma_wrapper_regs_PSLVERR
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);
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//--------------------------------------------------------------------------
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// CPU Bus interface logic
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//--------------------------------------------------------------------------
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logic cpuif_req;
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logic cpuif_wr_en;
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logic cpuif_rd_en;
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logic [8:0] cpuif_wr_addr;
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logic [8:0] cpuif_rd_addr;
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logic cpuif_wr_ack;
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logic cpuif_wr_err;
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logic [31:0] cpuif_wr_data;
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logic [3:0] cpuif_wr_byte_en;
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logic cpuif_rd_ack;
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logic cpuif_rd_err;
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logic [31:0] cpuif_rd_data;
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//--------------------------------------------------------------------------
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// Child instance signals
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//--------------------------------------------------------------------------
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typedef struct {
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logic pcie_top_regs;
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logic eth_dma_wrapper_regs;
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logic cpuif_err;
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} cpuif_sel_t;
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cpuif_sel_t cpuif_wr_sel;
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cpuif_sel_t cpuif_rd_sel;
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//--------------------------------------------------------------------------
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// Slave <-> Internal CPUIF <-> Master
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//--------------------------------------------------------------------------
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assign cpuif_req = s_apb_PSEL;
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assign cpuif_wr_en = s_apb_PWRITE;
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assign cpuif_rd_en = !s_apb_PWRITE;
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assign cpuif_wr_addr = s_apb_PADDR;
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assign cpuif_rd_addr = s_apb_PADDR;
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assign cpuif_wr_data = s_apb_PWDATA;
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assign cpuif_wr_byte_en = s_apb_PSTRB;
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assign s_apb_PRDATA = cpuif_rd_data;
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assign s_apb_PREADY = cpuif_rd_ack;
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assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
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//--------------------------------------------------------------------------
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// Fanout CPU Bus interface signals
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//--------------------------------------------------------------------------
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assign m_apb_pcie_top_regs_PSEL = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
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assign m_apb_pcie_top_regs_PENABLE = s_apb_PENABLE;
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assign m_apb_pcie_top_regs_PWRITE = cpuif_wr_sel.pcie_top_regs;
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assign m_apb_pcie_top_regs_PADDR = s_apb_PADDR[5:0];
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assign m_apb_pcie_top_regs_PPROT = s_apb_PPROT;
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assign m_apb_pcie_top_regs_PWDATA = cpuif_wr_data;
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assign m_apb_pcie_top_regs_PSTRB = cpuif_wr_byte_en;
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assign m_apb_eth_dma_wrapper_regs_PSEL = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
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assign m_apb_eth_dma_wrapper_regs_PENABLE = s_apb_PENABLE;
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assign m_apb_eth_dma_wrapper_regs_PWRITE = cpuif_wr_sel.eth_dma_wrapper_regs;
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assign m_apb_eth_dma_wrapper_regs_PADDR = s_apb_PADDR[7:0];
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assign m_apb_eth_dma_wrapper_regs_PPROT = s_apb_PPROT;
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assign m_apb_eth_dma_wrapper_regs_PWDATA = cpuif_wr_data;
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assign m_apb_eth_dma_wrapper_regs_PSTRB = cpuif_wr_byte_en;
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//--------------------------------------------------------------------------
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// Fanin CPU Bus interface signals
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//--------------------------------------------------------------------------
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always_comb begin
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cpuif_rd_ack = '0;
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cpuif_rd_err = '0;
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cpuif_rd_data = '0;
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if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
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cpuif_rd_ack = m_apb_pcie_top_regs_PREADY;
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cpuif_rd_err = m_apb_pcie_top_regs_PSLVERR;
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end
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if (cpuif_rd_sel.pcie_top_regs) begin
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cpuif_rd_data = m_apb_pcie_top_regs_PRDATA;
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end
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if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
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cpuif_rd_ack = m_apb_eth_dma_wrapper_regs_PREADY;
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cpuif_rd_err = m_apb_eth_dma_wrapper_regs_PSLVERR;
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end
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if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
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cpuif_rd_data = m_apb_eth_dma_wrapper_regs_PRDATA;
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end
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end
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//--------------------------------------------------------------------------
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// Write Address Decoder
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//--------------------------------------------------------------------------
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always_comb begin
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// Default all write select signals to 0
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cpuif_wr_sel = '{default: '0};
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if (cpuif_req && cpuif_wr_en) begin
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// A write request is pending
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if ((cpuif_wr_addr < (9'h38))) begin
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cpuif_wr_sel.pcie_top_regs = 1'b1;
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end
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else if ((cpuif_wr_addr >= (9'h100)) && (cpuif_wr_addr < (9'h1b8))) begin
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cpuif_wr_sel.eth_dma_wrapper_regs = 1'b1;
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end
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else begin
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cpuif_wr_sel.cpuif_err = 1'b1;
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end
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end else begin
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// No write request, all select signals remain 0
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end
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end
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//--------------------------------------------------------------------------
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// Read Address Decoder
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//--------------------------------------------------------------------------
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always_comb begin
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// Default all read select signals to 0
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cpuif_rd_sel = '{default: '0};
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if (cpuif_req && cpuif_rd_en) begin
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// A read request is pending
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if ((cpuif_rd_addr < (9'h38))) begin
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cpuif_rd_sel.pcie_top_regs = 1'b1;
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end
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else if ((cpuif_rd_addr >= (9'h100)) && (cpuif_rd_addr < (9'h1b8))) begin
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cpuif_rd_sel.eth_dma_wrapper_regs = 1'b1;
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end
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else begin
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cpuif_rd_sel.cpuif_err = 1'b1;
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end
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end else begin
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// No read request, all select signals remain 0
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end
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end
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endmodule
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