bslathi19/alibaba_pcie
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base: bslathi19:de33a46c780542dc7837a4f778140235be8268fb
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bslathi19:master bslathi19:reorg
...
compare: bslathi19:d9a25d0a7ac3b81ae90df67c9f6b2f8ed3d0d2c5
Branches Tags
bslathi19:master bslathi19:reorg

2 Commits
de33a46c78 ... d9a25d0a7a

Author SHA1 Message Date
Byron Lathi
d9a25d0a7a Get it kind of working again 2025-11-22 17:02:25 -08:00
Byron Lathi
85cb3cc2a6 Use taxi apb interface, finish reorg 2025-11-22 16:07:56 -08:00
16 changed files with 251 additions and 252 deletions
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2
requirements.txt
View File

@@ -7,4 +7,4 @@ rtl-manifest
build_fpga
fpga-sim
peakrdl
git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@dev/downsize_apb_paddr
git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb

12
sim/alibaba_pcie.py
View File

@@ -78,12 +78,12 @@ class TB:
# signals
user_clk=dut.clk_250,
user_reset=dut.rst_250,
user_lnk_up=dut.user_lnk_up,
user_lnk_up=dut.u_pcie_top.user_lnk_up,
rq_bus=AxiStreamBus.from_entity(dut.s_axis_rq),
rc_bus=AxiStreamBus.from_entity(dut.m_axis_rc),
cq_bus=AxiStreamBus.from_entity(dut.m_axis_cq),
cc_bus=AxiStreamBus.from_entity(dut.s_axis_cc),
rq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_rq),
rc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_rc),
cq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_cq),
cc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_cc),
)
self.dev.functions[0].configure_bar(0, 64*1024)
@@ -142,8 +142,6 @@ async def test_sanity(dut):
dev_bar0 = dev.bar_window[0]
tb.log.info(dev_bar0.write)
message = b"Hello, world! This is a long string of data with many letters and words."
await mem.write(0, message)

20
sources.list
View File

@@ -3,13 +3,15 @@ ip/taxi_eth_phy_25g_us_gty_ch/taxi_eth_phy_25g_us_gty_ch.xci
ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci
ip/taxi_eth_phy_25g_us_gty_ll_ch/taxi_eth_phy_25g_us_gty_ll_ch.xci
ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci
src/alibaba_cloud.xdc
src/alibaba_pcie_top.sv
src/regs/verilator.vlt
src/regs/pcie_dma_regs_pkg.sv
src/regs/pcie_dma_regs.sv
src/pcie_dma_wrapper.sv
src/eth/regs/eth_mac_25g_us_regs_pkg.sv
src/eth/regs/eth_mac_25g_us_regs.sv
src/eth/eth_dma_wrapper.sv
sub/taxi_sources.list
src/pcie/sources.list
src/eth/sources.list
src/regs/verilator.vlt
src/regs/alibaba_pcie_top_regs_pkg.sv
src/regs/alibaba_pcie_top_regs.sv
src/alibaba_pcie_top.sv
src/alibaba_cloud.xdc

41
src/alibaba_pcie_top.sv
View File

@@ -42,34 +42,26 @@ module alibaba_pcie(
);
logic clk_250;
logic rst_250;
taxi_axil_if m_axil_rd();
taxi_axil_if m_axil_wr();
taxi_apb_if #(.ADDR_W(9)) s_apb();
taxi_apb_if #(.ADDR_W(alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)) s_apb();
taxi_apb_if #(.ADDR_W(9)) m_apb[2]();
taxi_apb_if #(.ADDR_W(pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)) pcie_apb();
taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_apb();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
taxi_apb_interconnect #(
.M_CNT(2),
.ADDR_W(7),
.M_REGIONS(1),
.M_BASE_ADDR('0),
.M_ADDR_W({32'd6, 32'd6}),
.M_SECURE({2{1'b0}})
) u_apb_interconnect (
.clk (clk_250),
.rst (rst_250),
alibaba_pcie_top_regs u_alibaba_pcie_top_regs (
.s_apb (s_apb),
.m_apb (m_apb)
.m_apb_pcie_top_regs (pcie_apb),
.m_apb_eth_dma_wrapper_regs (eth_apb)
);
taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
.clk (clk_250),
.rst (rst_250),
@@ -96,14 +88,14 @@ eth_dma_wrapper u_eth_dma_wrapper (
.wr_dma_mst (dma_ram_eth_wr_if),
.rd_dma_mst (dma_ram_eth_rd_if),
.s_apb (m_apb[1])
.s_apb (eth_apb)
);
pcie_top u_pcie_top(
.pcie_exp_rxp (pcie_exp_rxp)
.pcie_exp_rxn (pcie_exp_rxn)
.pcie_exp_txp (pcie_exp_txp)
.pcie_exp_txn (pcie_exp_txn),
.pci_exp_rxp (pci_exp_rxp),
.pci_exp_rxn (pci_exp_rxn),
.pci_exp_txp (pci_exp_txp),
.pci_exp_txn (pci_exp_txn),
.pcie_mgt_refclk_p (pcie_mgt_refclk_p),
.pcie_mgt_refclk_n (pcie_mgt_refclk_n),
@@ -113,11 +105,16 @@ pcie_top u_pcie_top(
.user_lnk_up (Led_o[0]),
.phy_rdy_out (Led_o[1]),
.o_clk_250 (clk_250),
.o_rst_250 (rst_250),
.dma_ram_eth_wr_if (dma_ram_eth_wr_if),
.dma_ram_eth_rd_if (dma_ram_eth_rd_if),
.m_axil_rd (m_axil_rd),
.m_axil_wr (m_axil_wr)
.m_axil_wr (m_axil_wr),
.s_apb (pcie_apb)
);
endmodule

64
src/eth/eth_dma_wrapper.sv
View File

@@ -84,36 +84,44 @@ endgenerate
taxi_axis_if axis_sfp_stat();
taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb();
eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in;
eth_mac_25g_us_regs u_eth_mac_25g_us_regs (
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (s_apb_eth.psel),
.s_apb_penable (s_apb_eth.penable),
.s_apb_pwrite (s_apb_eth.pwrite),
.s_apb_pprot (s_apb_eth.pprot),
.s_apb_paddr (s_apb_eth.paddr),
.s_apb_pwdata (s_apb_eth.pwdata),
.s_apb_pstrb (s_apb_eth.pstrb),
.s_apb_pready (s_apb_eth.pready),
.s_apb_prdata (s_apb_eth.prdata),
.s_apb_pslverr (s_apb_eth.pslverr),
.s_apb_psel (eth_mac_apb.psel),
.s_apb_penable (eth_mac_apb.penable),
.s_apb_pwrite (eth_mac_apb.pwrite),
.s_apb_pprot (eth_mac_apb.pprot),
.s_apb_paddr (eth_mac_apb.paddr),
.s_apb_pwdata (eth_mac_apb.pwdata),
.s_apb_pstrb (eth_mac_apb.pstrb),
.s_apb_pready (eth_mac_apb.pready),
.s_apb_prdata (eth_mac_apb.prdata),
.s_apb_pslverr (eth_mac_apb.pslverr),
.hwif_in (hwif_in),
.hwif_out (hwif_out)
.hwif_in (hwif_in)
);
assign hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
logic rx_block_lock[2];
logic rx_status[2];
logic xcvr_qpll0lock_out;
logic xcvr_qpll1lock_out;
always_comb begin
hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next = xcvr_qpll0lock_out;
hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next = xcvr_qpll1lock_out;
for (int i = 0; i < 2; i++) begin
assign hwif_in.lane[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
assign hwif_in.lane[i].rx_status.rx_status.next = rx_status[i];
hwif_in.lanes[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
hwif_in.lanes[i].rx_status.rx_status.next = rx_status[i];
end
end
@@ -140,14 +148,14 @@ taxi_eth_mac_25g_us #(
.xcvr_qpll0pd_in (1'b0),
.xcvr_qpll0reset_in (1'b0),
.xcvr_qpll0pcierate_in (3'd0),
.xcvr_qpll0lock_out (hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next),
.xcvr_qpll0lock_out (xcvr_qpll0lock_out),
.xcvr_qpll0clk_out (),
.xcvr_qpll0refclk_out (),
.xcvr_gtrefclk01_in (sfp_mgt_refclk),
.xcvr_qpll1pd_in (1'b0),
.xcvr_qpll1reset_in (1'b0),
.xcvr_qpll1pcierate_in (3'd0),
.xcvr_qpll1lock_out (hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next),
.xcvr_qpll1lock_out (xcvr_qpll1lock_out),
.xcvr_qpll1clk_out (),
.xcvr_qpll1refclk_out (),
@@ -300,16 +308,16 @@ pcie_dma_regs u_pcie_dma_regs(
.clk (clk_250),
.rst (rst_250),
.s_apb_psel (s_apb_dma.psel),
.s_apb_penable (s_apb_dma.penable),
.s_apb_pwrite (s_apb_dma.pwrite),
.s_apb_pprot (s_apb_dma.pprot),
.s_apb_paddr (s_apb_dma.paddr),
.s_apb_pwdata (s_apb_dma.pwdata),
.s_apb_pstrb (s_apb_dma.pstrb),
.s_apb_pready (s_apb_dma.pready),
.s_apb_prdata (s_apb_dma.prdata),
.s_apb_pslverr (s_apb_dma.pslverr),
.s_apb_psel (eth_dma_apb.psel),
.s_apb_penable (eth_dma_apb.penable),
.s_apb_pwrite (eth_dma_apb.pwrite),
.s_apb_pprot (eth_dma_apb.pprot),
.s_apb_paddr (eth_dma_apb.paddr),
.s_apb_pwdata (eth_dma_apb.pwdata),
.s_apb_pstrb (eth_dma_apb.pstrb),
.s_apb_pready (eth_dma_apb.pready),
.s_apb_prdata (eth_dma_apb.prdata),
.s_apb_pslverr (eth_dma_apb.pslverr),
.hwif_in (dma_hwif_in),
.hwif_out (dma_hwif_out)

2
src/eth/regs/compile_regs.sh
View File

@@ -1,2 +1,2 @@
peakrdl regblock -t eth_mac_25g_us_regs eth_mac_25g_us_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl -o . --cpuif taxi-apb

116
src/eth/regs/eth_dma_wrapper_regs.sv
View File

@@ -11,42 +11,9 @@
module eth_dma_wrapper_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [7:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_eth_mac_25g_us_regs_PCLK,
output logic m_apb_eth_mac_25g_us_regs_PRESETn,
output logic m_apb_eth_mac_25g_us_regs_PSEL,
output logic m_apb_eth_mac_25g_us_regs_PENABLE,
output logic m_apb_eth_mac_25g_us_regs_PWRITE,
output logic [6:0] m_apb_eth_mac_25g_us_regs_PADDR,
output logic [2:0] m_apb_eth_mac_25g_us_regs_PPROT,
output logic [31:0] m_apb_eth_mac_25g_us_regs_PWDATA,
output logic [3:0] m_apb_eth_mac_25g_us_regs_PSTRB,
input logic [31:0] m_apb_eth_mac_25g_us_regs_PRDATA,
input logic m_apb_eth_mac_25g_us_regs_PREADY,
input logic m_apb_eth_mac_25g_us_regs_PSLVERR,
output logic m_apb_pcie_dma_regs_PCLK,
output logic m_apb_pcie_dma_regs_PRESETn,
output logic m_apb_pcie_dma_regs_PSEL,
output logic m_apb_pcie_dma_regs_PENABLE,
output logic m_apb_pcie_dma_regs_PWRITE,
output logic [5:0] m_apb_pcie_dma_regs_PADDR,
output logic [2:0] m_apb_pcie_dma_regs_PPROT,
output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
input logic [31:0] m_apb_pcie_dma_regs_PRDATA,
input logic m_apb_pcie_dma_regs_PREADY,
input logic m_apb_pcie_dma_regs_PSLVERR
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_eth_mac_25g_us_regs,
taxi_apb_if.mst m_apb_pcie_dma_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
@@ -81,38 +48,55 @@ module eth_dma_wrapper_regs (
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_eth_mac_25g_us_regs_PSEL = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs_PENABLE = s_apb_PENABLE;
assign m_apb_eth_mac_25g_us_regs_PWRITE = cpuif_wr_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs_PADDR = s_apb_PADDR[6:0];
assign m_apb_eth_mac_25g_us_regs_PPROT = s_apb_PPROT;
assign m_apb_eth_mac_25g_us_regs_PWDATA = cpuif_wr_data;
assign m_apb_eth_mac_25g_us_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_eth_mac_25g_us_regs.psel = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs.penable = s_apb.penable;
assign m_apb_eth_mac_25g_us_regs.pwrite = cpuif_wr_sel.eth_mac_25g_us_regs;
assign m_apb_eth_mac_25g_us_regs.paddr = s_apb.paddr;
assign m_apb_eth_mac_25g_us_regs.pprot = s_apb.pprot;
assign m_apb_eth_mac_25g_us_regs.pwdata = cpuif_wr_data;
assign m_apb_eth_mac_25g_us_regs.pstrb = cpuif_wr_byte_en;
assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.penable = s_apb.penable;
assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
@@ -122,18 +106,18 @@ module eth_dma_wrapper_regs (
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.eth_mac_25g_us_regs || cpuif_wr_sel.eth_mac_25g_us_regs) begin
cpuif_rd_ack = m_apb_eth_mac_25g_us_regs_PREADY;
cpuif_rd_err = m_apb_eth_mac_25g_us_regs_PSLVERR;
cpuif_rd_ack = m_apb_eth_mac_25g_us_regs.pready;
cpuif_rd_err = m_apb_eth_mac_25g_us_regs.pslverr;
end
if (cpuif_rd_sel.eth_mac_25g_us_regs) begin
cpuif_rd_data = m_apb_eth_mac_25g_us_regs_PRDATA;
cpuif_rd_data = m_apb_eth_mac_25g_us_regs.prdata;
end
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
end
end

6
src/eth/sources.list Normal file
View File

@@ -0,0 +1,6 @@
regs/eth_dma_wrapper_regs_pkg.sv
regs/eth_dma_wrapper_regs.sv
regs/eth_mac_25g_us_regs_pkg.sv
regs/eth_mac_25g_us_regs.sv
eth_dma_wrapper.sv

21
src/eth/pcie_top.sv → src/pcie/pcie_top.sv
View File

@@ -12,11 +12,16 @@ module pcie_top(
output wire user_lnk_up,
output wire phy_rdy_out,
output wire o_clk_250,
output wire o_rst_250,
taxi_dma_ram_if.wr_slv dma_ram_eth_wr_if,
taxi_dma_ram_if.rd_slv dma_ram_eth_rd_if,
taxi_axil_if.rd_mst m_axil_rd,
taxi_axil_if.wr_mst m_axil_wr
taxi_axil_if.wr_mst m_axil_wr,
taxi_apb_if.slv s_apb
);
@@ -27,8 +32,8 @@ logic rst_pcie;
logic clk_250;
logic rst_250;
logic user_lnk_up;
logic phy_rdy_out;
assign o_clk_250 = clk_250;
assign o_rst_250 = rst_250;
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
@@ -39,6 +44,9 @@ taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) pcie_dma_apb();
`ifndef SIM
IBUFDS_GTE4 m_ibufds (
.CEB('0),
@@ -49,6 +57,11 @@ IBUFDS_GTE4 m_ibufds (
);
`endif
pcie_top_regs u_pcie_top_regs (
.s_apb (s_apb),
.m_apb_pcie_dma_regs(pcie_dma_apb)
);
taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
.clk (clk_250),
.rst (rst_250),
@@ -96,7 +109,7 @@ pcie_dma_wrapper u_pcie_dma_wrapper (
.wr_dma_mst (dma_ram_pcie_wr_if),
.rd_dma_mst (dma_ram_pcie_rd_if),
.s_apb (m_apb[0])
.s_apb (pcie_dma_apb)
);
`ifndef SIM

2
src/pcie/regs/compile_regs.sh
View File

@@ -1,2 +1,2 @@
peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif apb4-flat
peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif taxi-apb

83
src/pcie/regs/pcie_top_regs.sv
View File

@@ -11,30 +11,8 @@
module pcie_top_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [5:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_pcie_dma_regs_PCLK,
output logic m_apb_pcie_dma_regs_PRESETn,
output logic m_apb_pcie_dma_regs_PSEL,
output logic m_apb_pcie_dma_regs_PENABLE,
output logic m_apb_pcie_dma_regs_PWRITE,
output logic [5:0] m_apb_pcie_dma_regs_PADDR,
output logic [2:0] m_apb_pcie_dma_regs_PPROT,
output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
input logic [31:0] m_apb_pcie_dma_regs_PRDATA,
input logic m_apb_pcie_dma_regs_PREADY,
input logic m_apb_pcie_dma_regs_PSLVERR
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_pcie_dma_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
@@ -68,31 +46,48 @@ module pcie_top_regs (
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.penable = s_apb.penable;
assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
@@ -102,11 +97,11 @@ module pcie_top_regs (
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
end
if (cpuif_rd_sel.pcie_dma_regs) begin
cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
end
end

9
src/pcie/sources.list Normal file
View File

@@ -0,0 +1,9 @@
regs/verilator.vlt
regs/pcie_dma_regs_pkg.sv
regs/pcie_dma_regs.sv
regs/pcie_top_regs_pkg.sv
regs/pcie_top_regs.sv
pcie_dma_wrapper.sv
pcie_top.sv

116
src/regs/alibaba_pcie_top_regs.sv
View File

@@ -11,42 +11,9 @@
module alibaba_pcie_top_regs (
input logic s_apb_PCLK,
input logic s_apb_PRESETn,
input logic s_apb_PSEL,
input logic s_apb_PENABLE,
input logic s_apb_PWRITE,
input logic [8:0] s_apb_PADDR,
input logic [2:0] s_apb_PPROT,
input logic [31:0] s_apb_PWDATA,
input logic [3:0] s_apb_PSTRB,
output logic [31:0] s_apb_PRDATA,
output logic s_apb_PREADY,
output logic s_apb_PSLVERR,
output logic m_apb_pcie_top_regs_PCLK,
output logic m_apb_pcie_top_regs_PRESETn,
output logic m_apb_pcie_top_regs_PSEL,
output logic m_apb_pcie_top_regs_PENABLE,
output logic m_apb_pcie_top_regs_PWRITE,
output logic [5:0] m_apb_pcie_top_regs_PADDR,
output logic [2:0] m_apb_pcie_top_regs_PPROT,
output logic [31:0] m_apb_pcie_top_regs_PWDATA,
output logic [3:0] m_apb_pcie_top_regs_PSTRB,
input logic [31:0] m_apb_pcie_top_regs_PRDATA,
input logic m_apb_pcie_top_regs_PREADY,
input logic m_apb_pcie_top_regs_PSLVERR,
output logic m_apb_eth_dma_wrapper_regs_PCLK,
output logic m_apb_eth_dma_wrapper_regs_PRESETn,
output logic m_apb_eth_dma_wrapper_regs_PSEL,
output logic m_apb_eth_dma_wrapper_regs_PENABLE,
output logic m_apb_eth_dma_wrapper_regs_PWRITE,
output logic [7:0] m_apb_eth_dma_wrapper_regs_PADDR,
output logic [2:0] m_apb_eth_dma_wrapper_regs_PPROT,
output logic [31:0] m_apb_eth_dma_wrapper_regs_PWDATA,
output logic [3:0] m_apb_eth_dma_wrapper_regs_PSTRB,
input logic [31:0] m_apb_eth_dma_wrapper_regs_PRDATA,
input logic m_apb_eth_dma_wrapper_regs_PREADY,
input logic m_apb_eth_dma_wrapper_regs_PSLVERR
taxi_apb_if.slv s_apb,
taxi_apb_if.mst m_apb_pcie_top_regs,
taxi_apb_if.mst m_apb_eth_dma_wrapper_regs
);
//--------------------------------------------------------------------------
// CPU Bus interface logic
@@ -81,38 +48,55 @@ module alibaba_pcie_top_regs (
// Slave <-> Internal CPUIF <-> Master
//--------------------------------------------------------------------------
`ifndef SYNTHESIS
initial begin
assert_bad_addr_width: assert($bits(s_apb.paddr) >= alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)
else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH);
assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH)
else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH);
end
`ifdef PEAKRDL_ASSERTIONS
assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
`endif
`endif
assign cpuif_req = s_apb_PSEL;
assign cpuif_wr_en = s_apb_PWRITE;
assign cpuif_rd_en = !s_apb_PWRITE;
assign cpuif_req = s_apb.psel;
assign cpuif_wr_en = s_apb.pwrite;
assign cpuif_rd_en = !s_apb.pwrite;
assign cpuif_wr_addr = s_apb_PADDR;
assign cpuif_rd_addr = s_apb_PADDR;
assign cpuif_wr_addr = s_apb.paddr;
assign cpuif_rd_addr = s_apb.paddr;
assign cpuif_wr_data = s_apb_PWDATA;
assign cpuif_wr_byte_en = s_apb_PSTRB;
assign cpuif_wr_data = s_apb.pwdata;
assign cpuif_wr_byte_en = s_apb.pstrb;
assign s_apb_PRDATA = cpuif_rd_data;
assign s_apb_PREADY = cpuif_rd_ack;
assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
assign s_apb.prdata = cpuif_rd_data;
assign s_apb.pready = cpuif_rd_ack;
assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
//--------------------------------------------------------------------------
// Fanout CPU Bus interface signals
//--------------------------------------------------------------------------
assign m_apb_pcie_top_regs_PSEL = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
assign m_apb_pcie_top_regs_PENABLE = s_apb_PENABLE;
assign m_apb_pcie_top_regs_PWRITE = cpuif_wr_sel.pcie_top_regs;
assign m_apb_pcie_top_regs_PADDR = s_apb_PADDR[5:0];
assign m_apb_pcie_top_regs_PPROT = s_apb_PPROT;
assign m_apb_pcie_top_regs_PWDATA = cpuif_wr_data;
assign m_apb_pcie_top_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_eth_dma_wrapper_regs_PSEL = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs_PENABLE = s_apb_PENABLE;
assign m_apb_eth_dma_wrapper_regs_PWRITE = cpuif_wr_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs_PADDR = s_apb_PADDR[7:0];
assign m_apb_eth_dma_wrapper_regs_PPROT = s_apb_PPROT;
assign m_apb_eth_dma_wrapper_regs_PWDATA = cpuif_wr_data;
assign m_apb_eth_dma_wrapper_regs_PSTRB = cpuif_wr_byte_en;
assign m_apb_pcie_top_regs.psel = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
assign m_apb_pcie_top_regs.penable = s_apb.penable;
assign m_apb_pcie_top_regs.pwrite = cpuif_wr_sel.pcie_top_regs;
assign m_apb_pcie_top_regs.paddr = s_apb.paddr;
assign m_apb_pcie_top_regs.pprot = s_apb.pprot;
assign m_apb_pcie_top_regs.pwdata = cpuif_wr_data;
assign m_apb_pcie_top_regs.pstrb = cpuif_wr_byte_en;
assign m_apb_eth_dma_wrapper_regs.psel = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs.penable = s_apb.penable;
assign m_apb_eth_dma_wrapper_regs.pwrite = cpuif_wr_sel.eth_dma_wrapper_regs;
assign m_apb_eth_dma_wrapper_regs.paddr = s_apb.paddr;
assign m_apb_eth_dma_wrapper_regs.pprot = s_apb.pprot;
assign m_apb_eth_dma_wrapper_regs.pwdata = cpuif_wr_data;
assign m_apb_eth_dma_wrapper_regs.pstrb = cpuif_wr_byte_en;
//--------------------------------------------------------------------------
// Intermediate signals for interface array fanin
//--------------------------------------------------------------------------
//--------------------------------------------------------------------------
// Fanin CPU Bus interface signals
@@ -122,18 +106,18 @@ module alibaba_pcie_top_regs (
cpuif_rd_err = '0;
cpuif_rd_data = '0;
if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
cpuif_rd_ack = m_apb_pcie_top_regs_PREADY;
cpuif_rd_err = m_apb_pcie_top_regs_PSLVERR;
cpuif_rd_ack = m_apb_pcie_top_regs.pready;
cpuif_rd_err = m_apb_pcie_top_regs.pslverr;
end
if (cpuif_rd_sel.pcie_top_regs) begin
cpuif_rd_data = m_apb_pcie_top_regs_PRDATA;
cpuif_rd_data = m_apb_pcie_top_regs.prdata;
end
if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
cpuif_rd_ack = m_apb_eth_dma_wrapper_regs_PREADY;
cpuif_rd_err = m_apb_eth_dma_wrapper_regs_PSLVERR;
cpuif_rd_ack = m_apb_eth_dma_wrapper_regs.pready;
cpuif_rd_err = m_apb_eth_dma_wrapper_regs.pslverr;
end
if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
cpuif_rd_data = m_apb_eth_dma_wrapper_regs_PRDATA;
cpuif_rd_data = m_apb_eth_dma_wrapper_regs.prdata;
end
end

3
src/regs/compile_regs.sh
View File

@@ -1,4 +1,3 @@
SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif apb4-flat
peakrdl c-header -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.h
peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb

4
src/regs/verilator.vlt Normal file
View File

@@ -0,0 +1,4 @@
`verilator_config
lint_off -rule MULTIDRIVEN -file "**/regs/*"
lint_off -file "**/regs/*"

2
sub/taxi

Submodule sub/taxi updated: 729bf79427...2391e4f366