Add more register printout

requirements.txt

@@ -7,4 +7,5 @@ rtl-manifest
 build_fpga
 fpga-sim
 peakrdl
-git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@dev/downsize_apb_paddr
+peakrdl-python-regmap
+git+https://git.byronlathi.com/bslathi19/PeakRDL-BusDecoder.git@taxi_apb

sim/alibaba_pcie.py

@@ -10,6 +10,8 @@ from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
 
 from baser import BaseRSerdesSource, BaseRSerdesSink
 
+from alibaba_pcie_top_regs import alibaba_pcie_top_regsClass
+
 CLK_PERIOD = 4
 
 class TB:
@@ -76,14 +78,14 @@ class TB:
             pf3_msix_pba_offset=0x00000000,
 
             # signals
-            user_clk=dut.clk_250,
-            user_reset=dut.rst_250,
-            user_lnk_up=dut.user_lnk_up,
+            user_clk=dut.u_pcie_top.clk_250,
+            user_reset=dut.u_pcie_top.rst_250,
+            user_lnk_up=dut.u_pcie_top.user_lnk_up,
 
-            rq_bus=AxiStreamBus.from_entity(dut.s_axis_rq),
-            rc_bus=AxiStreamBus.from_entity(dut.m_axis_rc),
-            cq_bus=AxiStreamBus.from_entity(dut.m_axis_cq),
-            cc_bus=AxiStreamBus.from_entity(dut.s_axis_cc),
+            rq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_rq),
+            rc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_rc),
+            cq_bus=AxiStreamBus.from_entity(dut.u_pcie_top.m_axis_cq),
+            cc_bus=AxiStreamBus.from_entity(dut.u_pcie_top.s_axis_cc),
         )
 
         self.dev.functions[0].configure_bar(0, 64*1024)
@@ -142,31 +144,40 @@ async def test_sanity(dut):
 
     dev_bar0 = dev.bar_window[0]
 
-    tb.log.info(dev_bar0.write)
-
     message = b"Hello, world! This is a long string of data with many letters and words."
 
     await mem.write(0, message)
 
-    await dev_bar0.write_dword(0x0, 0x00000000)
-    await dev_bar0.write_dword(0x4, 0x00000000)
-    await dev_bar0.write_dword(0x8, 0x00000000)
-    await dev_bar0.write_dword(0xc, len(message))
-    await dev_bar0.write_dword(0x10, 0x00000001)
+    regmap = alibaba_pcie_top_regsClass()
+    pcie_dma_rd = regmap.pcie_top_regs.pcie_dma_regs.dma_rd
+    pcie_dma_wr = regmap.pcie_top_regs.pcie_dma_regs.dma_wr
+
+    eth_dma_rd = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_rd
+    eth_dma_wr = regmap.eth_dma_wrapper_regs.pcie_dma_regs.dma_wr
+
+
+    # DMA from host to dma memory
+    await dev_bar0.write_dword(pcie_dma_rd.src_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.src_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.dst_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_rd.length.addr, len(message))
+    await dev_bar0.write_dword(pcie_dma_rd.trigger.addr, 0x00000001)
 
     await Timer(1, "us")
 
-    await dev_bar0.write_dword(0x40, 0x00000000)
-    await dev_bar0.write_dword(0x44, 0x00000000)
-    await dev_bar0.write_dword(0x48, 0x00000000)
-    await dev_bar0.write_dword(0x4c, len(message))
-    await dev_bar0.write_dword(0x50, 0x00000001)
+    # Set up stream to memory DMA to store ethernet frame
+    await dev_bar0.write_dword(eth_dma_wr.src_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.dst_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.dst_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_wr.length.addr, len(message))
+    await dev_bar0.write_dword(eth_dma_wr.trigger.addr, 0x00000001)
 
-    await dev_bar0.write_dword(0x60, 0x00000000)
-    await dev_bar0.write_dword(0x64, 0x00000000)
-    await dev_bar0.write_dword(0x68, 0x00000000)
-    await dev_bar0.write_dword(0x6c, len(message))
-    await dev_bar0.write_dword(0x70, 0x00000001)
+    # Trigger memory to stream dma to send ethernet frame
+    await dev_bar0.write_dword(eth_dma_rd.src_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.src_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.dst_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(eth_dma_rd.length.addr, len(message))
+    await dev_bar0.write_dword(eth_dma_rd.trigger.addr, 0x00000001)
 
     rx_frame = await tb.serdes_sinks[0].recv()
 
@@ -176,11 +187,12 @@ async def test_sanity(dut):
 
     await Timer(1, "us")
 
-    await dev_bar0.write_dword(0x20, 0x00000100)
-    await dev_bar0.write_dword(0x24, 0x00000000)
-    await dev_bar0.write_dword(0x28, 0x00000000)
-    await dev_bar0.write_dword(0x2c, len(message))
-    await dev_bar0.write_dword(0x30, 0x00000001)
+    # DMA from dma memory to host
+    await dev_bar0.write_dword(pcie_dma_wr.src_addr.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.dst_addr_low.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.dst_addr_high.addr, 0x00000000)
+    await dev_bar0.write_dword(pcie_dma_wr.length.addr, len(message))
+    await dev_bar0.write_dword(pcie_dma_wr.trigger.addr, 0x00000001)
 
     await Timer(1, "us")
 

sim/alibaba_pcie_top_regs.py

@@ -0,0 +1 @@
+../src/regs/alibaba_pcie_top_regs.py

sources.list

@@ -3,13 +3,15 @@ ip/taxi_eth_phy_25g_us_gty_ch/taxi_eth_phy_25g_us_gty_ch.xci
 ip/taxi_eth_phy_25g_us_gty_full/taxi_eth_phy_25g_us_gty_full.xci
 ip/taxi_eth_phy_25g_us_gty_ll_ch/taxi_eth_phy_25g_us_gty_ll_ch.xci
 ip/taxi_eth_phy_25g_us_gty_ll_full/taxi_eth_phy_25g_us_gty_ll_full.xci
-src/alibaba_cloud.xdc
-src/alibaba_pcie_top.sv
-src/regs/verilator.vlt
-src/regs/pcie_dma_regs_pkg.sv
-src/regs/pcie_dma_regs.sv
-src/pcie_dma_wrapper.sv
-src/eth/regs/eth_mac_25g_us_regs_pkg.sv
-src/eth/regs/eth_mac_25g_us_regs.sv
-src/eth/eth_dma_wrapper.sv
+
 sub/taxi_sources.list
+
+src/pcie/sources.list
+src/eth/sources.list
+
+src/regs/verilator.vlt
+src/regs/alibaba_pcie_top_regs_pkg.sv
+src/regs/alibaba_pcie_top_regs.sv
+src/alibaba_pcie_top.sv
+
+src/alibaba_cloud.xdc

src/alibaba_pcie_top.sv

@@ -42,34 +42,26 @@ module alibaba_pcie(
 );
 
 
+logic clk_250;
+logic rst_250;
 
 taxi_axil_if m_axil_rd();
 taxi_axil_if m_axil_wr();
 
-taxi_apb_if #(.ADDR_W(9)) s_apb();
+taxi_apb_if #(.ADDR_W(alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)) s_apb();
 
-taxi_apb_if #(.ADDR_W(9)) m_apb[2]();
+taxi_apb_if #(.ADDR_W(pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)) pcie_apb();
+taxi_apb_if #(.ADDR_W(eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)) eth_apb();
 
 taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_rd_if();
 taxi_dma_ram_if #(.SEGS(4)) dma_ram_eth_wr_if();
 
-taxi_apb_interconnect #(
-    .M_CNT(2),
-    .ADDR_W(7),
-    .M_REGIONS(1),
-    .M_BASE_ADDR('0),
-    .M_ADDR_W({32'd6, 32'd6}),
-    .M_SECURE({2{1'b0}})
-) u_apb_interconnect (
-    .clk                            (clk_250),
-    .rst                            (rst_250),
-
+alibaba_pcie_top_regs u_alibaba_pcie_top_regs (
     .s_apb                          (s_apb),
-
-    .m_apb                          (m_apb)
+    .m_apb_pcie_top_regs            (pcie_apb),
+    .m_apb_eth_dma_wrapper_regs     (eth_apb)
 );
 
-
 taxi_axil_apb_adapter u_taxi_axil_apb_adapter (
     .clk                (clk_250),
     .rst                (rst_250),
@@ -96,14 +88,14 @@ eth_dma_wrapper u_eth_dma_wrapper (
     .wr_dma_mst         (dma_ram_eth_wr_if),
     .rd_dma_mst         (dma_ram_eth_rd_if),
 
-    .s_apb              (m_apb[1])
+    .s_apb              (eth_apb)
 );
 
 pcie_top u_pcie_top(
-    .pcie_exp_rxp       (pcie_exp_rxp)
-    .pcie_exp_rxn       (pcie_exp_rxn)
-    .pcie_exp_txp       (pcie_exp_txp)
-    .pcie_exp_txn       (pcie_exp_txn),
+    .pci_exp_rxp        (pci_exp_rxp),
+    .pci_exp_rxn        (pci_exp_rxn),
+    .pci_exp_txp        (pci_exp_txp),
+    .pci_exp_txn        (pci_exp_txn),
 
     .pcie_mgt_refclk_p  (pcie_mgt_refclk_p),
     .pcie_mgt_refclk_n  (pcie_mgt_refclk_n),
@@ -113,11 +105,16 @@ pcie_top u_pcie_top(
     .user_lnk_up        (Led_o[0]),
     .phy_rdy_out        (Led_o[1]),
 
+    .o_clk_250          (clk_250),
+    .o_rst_250          (rst_250),
+
     .dma_ram_eth_wr_if  (dma_ram_eth_wr_if),
     .dma_ram_eth_rd_if  (dma_ram_eth_rd_if),
 
     .m_axil_rd          (m_axil_rd),
-    .m_axil_wr          (m_axil_wr)
+    .m_axil_wr          (m_axil_wr),
+
+    .s_apb              (pcie_apb)
 );
 
 endmodule

src/eth/eth_dma_wrapper.sv

@@ -84,36 +84,49 @@ endgenerate
 
 taxi_axis_if axis_sfp_stat();
 
+taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) eth_dma_apb();
+taxi_apb_if #(.ADDR_W(eth_mac_25g_us_regs_pkg::ETH_MAC_25G_US_REGS_MIN_ADDR_WIDTH)) eth_mac_apb();
+
+eth_dma_wrapper_regs u_eth_dma_wrapper_regs (
+    .s_apb                          (s_apb),
+    .m_apb_eth_mac_25g_us_regs      (eth_mac_apb),
+    .m_apb_pcie_dma_regs            (eth_dma_apb)
+);
+
 eth_mac_25g_us_regs_pkg::eth_mac_25g_us_regs__in_t hwif_in;
 
 eth_mac_25g_us_regs u_eth_mac_25g_us_regs (
     .clk                            (clk_250),
     .rst                            (rst_250),
 
-    .s_apb_psel                     (s_apb_eth.psel),
-    .s_apb_penable                  (s_apb_eth.penable),
-    .s_apb_pwrite                   (s_apb_eth.pwrite),
-    .s_apb_pprot                    (s_apb_eth.pprot),
-    .s_apb_paddr                    (s_apb_eth.paddr),
-    .s_apb_pwdata                   (s_apb_eth.pwdata),
-    .s_apb_pstrb                    (s_apb_eth.pstrb),
-    .s_apb_pready                   (s_apb_eth.pready),
-    .s_apb_prdata                   (s_apb_eth.prdata),
-    .s_apb_pslverr                  (s_apb_eth.pslverr),
+    .s_apb_psel                     (eth_mac_apb.psel),
+    .s_apb_penable                  (eth_mac_apb.penable),
+    .s_apb_pwrite                   (eth_mac_apb.pwrite),
+    .s_apb_pprot                    (eth_mac_apb.pprot),
+    .s_apb_paddr                    (eth_mac_apb.paddr),
+    .s_apb_pwdata                   (eth_mac_apb.pwdata),
+    .s_apb_pstrb                    (eth_mac_apb.pstrb),
+    .s_apb_pready                   (eth_mac_apb.pready),
+    .s_apb_prdata                   (eth_mac_apb.prdata),
+    .s_apb_pslverr                  (eth_mac_apb.pslverr),
 
-    .hwif_in                        (hwif_in),
-    .hwif_out                       (hwif_out)
+    .hwif_in                        (hwif_in)
 );
 
-assign hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
-
 logic rx_block_lock[2];
 logic rx_status[2];
 
+logic xcvr_qpll0lock_out;
+logic xcvr_qpll1lock_out;
+
 always_comb begin
+    hwif_in.common.xcvr_gtpowergood_out.xcvr_gtpowergood_out.next = xcvr_gtpowergood;
+    hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next = xcvr_qpll0lock_out;
+    hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next = xcvr_qpll1lock_out;
+
     for (int i = 0; i < 2; i++) begin
-        assign hwif_in.lane[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
-        assign hwif_in.lane[i].rx_status.rx_status.next = rx_status[i];
+        hwif_in.lanes[i].rx_block_lock.rx_block_lock.next = rx_block_lock[i];
+        hwif_in.lanes[i].rx_status.rx_status.next = rx_status[i];
     end
 end
 
@@ -140,14 +153,14 @@ taxi_eth_mac_25g_us #(
     .xcvr_qpll0pd_in                    (1'b0),
     .xcvr_qpll0reset_in                 (1'b0),
     .xcvr_qpll0pcierate_in              (3'd0),
-    .xcvr_qpll0lock_out                 (hwif_in.common.xcvr_qpll0lock_out.xcvr_qpll0lock_out.next),
+    .xcvr_qpll0lock_out                 (xcvr_qpll0lock_out),
     .xcvr_qpll0clk_out                  (),
     .xcvr_qpll0refclk_out               (),
     .xcvr_gtrefclk01_in                 (sfp_mgt_refclk),
     .xcvr_qpll1pd_in                    (1'b0),
     .xcvr_qpll1reset_in                 (1'b0),
     .xcvr_qpll1pcierate_in              (3'd0),
-    .xcvr_qpll1lock_out                 (hwif_in.common.xcvr_qpll1lock_out.xcvr_qpll1lock_out.next),
+    .xcvr_qpll1lock_out                 (xcvr_qpll1lock_out),
     .xcvr_qpll1clk_out                  (),
     .xcvr_qpll1refclk_out               (),
 
@@ -300,16 +313,16 @@ pcie_dma_regs u_pcie_dma_regs(
     .clk                            (clk_250),
     .rst                            (rst_250),
 
-    .s_apb_psel                     (s_apb_dma.psel),
-    .s_apb_penable                  (s_apb_dma.penable),
-    .s_apb_pwrite                   (s_apb_dma.pwrite),
-    .s_apb_pprot                    (s_apb_dma.pprot),
-    .s_apb_paddr                    (s_apb_dma.paddr),
-    .s_apb_pwdata                   (s_apb_dma.pwdata),
-    .s_apb_pstrb                    (s_apb_dma.pstrb),
-    .s_apb_pready                   (s_apb_dma.pready),
-    .s_apb_prdata                   (s_apb_dma.prdata),
-    .s_apb_pslverr                  (s_apb_dma.pslverr),
+    .s_apb_psel                     (eth_dma_apb.psel),
+    .s_apb_penable                  (eth_dma_apb.penable),
+    .s_apb_pwrite                   (eth_dma_apb.pwrite),
+    .s_apb_pprot                    (eth_dma_apb.pprot),
+    .s_apb_paddr                    (eth_dma_apb.paddr),
+    .s_apb_pwdata                   (eth_dma_apb.pwdata),
+    .s_apb_pstrb                    (eth_dma_apb.pstrb),
+    .s_apb_pready                   (eth_dma_apb.pready),
+    .s_apb_prdata                   (eth_dma_apb.prdata),
+    .s_apb_pslverr                  (eth_dma_apb.pslverr),
 
     .hwif_in                        (dma_hwif_in),
     .hwif_out                       (dma_hwif_out)

src/eth/regs/compile_regs.sh

@@ -1,2 +1,2 @@
 peakrdl regblock -t eth_mac_25g_us_regs eth_mac_25g_us_regs.rdl -o . --cpuif apb4-flat
-peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl  -o . --cpuif apb4-flat
+peakrdl busdecoder -t eth_dma_wrapper_regs eth_mac_25g_us_regs.rdl ../../pcie/regs/pcie_dma_regs.rdl eth_dma_wrapper_regs.rdl  -o . --cpuif taxi-apb

src/eth/regs/eth_dma_wrapper_regs.sv

@@ -11,42 +11,9 @@
 
 
 module eth_dma_wrapper_regs (
-    input  logic s_apb_PCLK,
-    input  logic s_apb_PRESETn,
-    input  logic s_apb_PSEL,
-    input  logic s_apb_PENABLE,
-    input  logic s_apb_PWRITE,
-    input  logic [7:0] s_apb_PADDR,
-    input  logic [2:0] s_apb_PPROT,
-    input  logic [31:0] s_apb_PWDATA,
-    input  logic [3:0] s_apb_PSTRB,
-    output logic [31:0] s_apb_PRDATA,
-    output logic s_apb_PREADY,
-    output logic s_apb_PSLVERR,
-    output logic m_apb_eth_mac_25g_us_regs_PCLK,
-    output logic m_apb_eth_mac_25g_us_regs_PRESETn,
-    output logic m_apb_eth_mac_25g_us_regs_PSEL,
-    output logic m_apb_eth_mac_25g_us_regs_PENABLE,
-    output logic m_apb_eth_mac_25g_us_regs_PWRITE,
-    output logic [6:0] m_apb_eth_mac_25g_us_regs_PADDR,
-    output logic [2:0] m_apb_eth_mac_25g_us_regs_PPROT,
-    output logic [31:0] m_apb_eth_mac_25g_us_regs_PWDATA,
-    output logic [3:0] m_apb_eth_mac_25g_us_regs_PSTRB,
-    input  logic [31:0] m_apb_eth_mac_25g_us_regs_PRDATA,
-    input  logic m_apb_eth_mac_25g_us_regs_PREADY,
-    input  logic m_apb_eth_mac_25g_us_regs_PSLVERR,
-    output logic m_apb_pcie_dma_regs_PCLK,
-    output logic m_apb_pcie_dma_regs_PRESETn,
-    output logic m_apb_pcie_dma_regs_PSEL,
-    output logic m_apb_pcie_dma_regs_PENABLE,
-    output logic m_apb_pcie_dma_regs_PWRITE,
-    output logic [5:0] m_apb_pcie_dma_regs_PADDR,
-    output logic [2:0] m_apb_pcie_dma_regs_PPROT,
-    output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
-    output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
-    input  logic [31:0] m_apb_pcie_dma_regs_PRDATA,
-    input  logic m_apb_pcie_dma_regs_PREADY,
-    input  logic m_apb_pcie_dma_regs_PSLVERR
+    taxi_apb_if.slv s_apb,
+    taxi_apb_if.mst m_apb_eth_mac_25g_us_regs,
+    taxi_apb_if.mst m_apb_pcie_dma_regs
 );
     //--------------------------------------------------------------------------
     // CPU Bus interface logic
@@ -81,38 +48,55 @@ module eth_dma_wrapper_regs (
     // Slave <-> Internal CPUIF <-> Master
     //--------------------------------------------------------------------------
     
+    `ifndef SYNTHESIS
+        initial begin
+            assert_bad_addr_width: assert($bits(s_apb.paddr) >= eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH)
+                else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_MIN_ADDR_WIDTH);
+            assert_bad_data_width: assert($bits(s_apb.pwdata) == eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH)
+                else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), eth_dma_wrapper_regs_pkg::ETH_DMA_WRAPPER_REGS_DATA_WIDTH);
+        end
+        `ifdef PEAKRDL_ASSERTIONS
+        assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
+            else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
+    `endif
 
-    assign cpuif_req   = s_apb_PSEL;
-    assign cpuif_wr_en = s_apb_PWRITE;
-    assign cpuif_rd_en = !s_apb_PWRITE;
+    assign cpuif_req   = s_apb.psel;
+    assign cpuif_wr_en = s_apb.pwrite;
+    assign cpuif_rd_en = !s_apb.pwrite;
 
-    assign cpuif_wr_addr = s_apb_PADDR;
-    assign cpuif_rd_addr = s_apb_PADDR;
+    assign cpuif_wr_addr = s_apb.paddr;
+    assign cpuif_rd_addr = s_apb.paddr;
 
-    assign cpuif_wr_data = s_apb_PWDATA;
-    assign cpuif_wr_byte_en = s_apb_PSTRB;
+    assign cpuif_wr_data = s_apb.pwdata;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
 
-    assign s_apb_PRDATA = cpuif_rd_data;
-    assign s_apb_PREADY = cpuif_rd_ack;
-    assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+    assign s_apb.prdata = cpuif_rd_data;
+    assign s_apb.pready = cpuif_rd_ack;
+    assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
 
     //--------------------------------------------------------------------------
     // Fanout CPU Bus interface signals
     //--------------------------------------------------------------------------
-    assign m_apb_eth_mac_25g_us_regs_PSEL = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
-    assign m_apb_eth_mac_25g_us_regs_PENABLE = s_apb_PENABLE;
-    assign m_apb_eth_mac_25g_us_regs_PWRITE = cpuif_wr_sel.eth_mac_25g_us_regs;
-    assign m_apb_eth_mac_25g_us_regs_PADDR = s_apb_PADDR[6:0];
-    assign m_apb_eth_mac_25g_us_regs_PPROT = s_apb_PPROT;
-    assign m_apb_eth_mac_25g_us_regs_PWDATA = cpuif_wr_data;
-    assign m_apb_eth_mac_25g_us_regs_PSTRB = cpuif_wr_byte_en;
-    assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
-    assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
-    assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
-    assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
-    assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
-    assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
-    assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
+    assign m_apb_eth_mac_25g_us_regs.psel = cpuif_wr_sel.eth_mac_25g_us_regs|cpuif_rd_sel.eth_mac_25g_us_regs;
+    assign m_apb_eth_mac_25g_us_regs.penable = s_apb.penable;
+    assign m_apb_eth_mac_25g_us_regs.pwrite = cpuif_wr_sel.eth_mac_25g_us_regs;
+    assign m_apb_eth_mac_25g_us_regs.paddr = s_apb.paddr;
+    assign m_apb_eth_mac_25g_us_regs.pprot = s_apb.pprot;
+    assign m_apb_eth_mac_25g_us_regs.pwdata = cpuif_wr_data;
+    assign m_apb_eth_mac_25g_us_regs.pstrb = cpuif_wr_byte_en;
+    assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.penable = s_apb.penable;
+    assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
+    assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
+    assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
+    assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
+
+    //--------------------------------------------------------------------------
+    // Intermediate signals for interface array fanin
+    //--------------------------------------------------------------------------
+
 
     //--------------------------------------------------------------------------
     // Fanin CPU Bus interface signals
@@ -122,18 +106,18 @@ module eth_dma_wrapper_regs (
         cpuif_rd_err = '0;
         cpuif_rd_data = '0;
         if (cpuif_rd_sel.eth_mac_25g_us_regs || cpuif_wr_sel.eth_mac_25g_us_regs) begin
-            cpuif_rd_ack = m_apb_eth_mac_25g_us_regs_PREADY;
-            cpuif_rd_err = m_apb_eth_mac_25g_us_regs_PSLVERR;
+            cpuif_rd_ack = m_apb_eth_mac_25g_us_regs.pready;
+            cpuif_rd_err = m_apb_eth_mac_25g_us_regs.pslverr;
         end
         if (cpuif_rd_sel.eth_mac_25g_us_regs) begin
-            cpuif_rd_data = m_apb_eth_mac_25g_us_regs_PRDATA;
+            cpuif_rd_data = m_apb_eth_mac_25g_us_regs.prdata;
         end
         if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
-            cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
-            cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
+            cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
+            cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
         end
         if (cpuif_rd_sel.pcie_dma_regs) begin
-            cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
+            cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
         end
     end
 

src/eth/sources.list

@@ -0,0 +1,6 @@
+regs/eth_dma_wrapper_regs_pkg.sv
+regs/eth_dma_wrapper_regs.sv
+regs/eth_mac_25g_us_regs_pkg.sv
+regs/eth_mac_25g_us_regs.sv
+
+eth_dma_wrapper.sv

src/pcie/pcie_top.sv

@@ -12,11 +12,16 @@ module pcie_top(
     output wire                     user_lnk_up,
     output wire                     phy_rdy_out,
 
+    output wire                     o_clk_250,
+    output wire                     o_rst_250,
+
     taxi_dma_ram_if.wr_slv          dma_ram_eth_wr_if,
     taxi_dma_ram_if.rd_slv          dma_ram_eth_rd_if,
 
     taxi_axil_if.rd_mst             m_axil_rd,
-    taxi_axil_if.wr_mst             m_axil_wr
+    taxi_axil_if.wr_mst             m_axil_wr,
+
+    taxi_apb_if.slv                 s_apb
 
 );
 
@@ -27,8 +32,8 @@ logic rst_pcie;
 logic clk_250;
 logic rst_250;
 
-logic user_lnk_up;
-logic phy_rdy_out;
+assign o_clk_250 = clk_250;
+assign o_rst_250 = rst_250;
 
 taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(33), .KEEP_W(8)) s_axis_cc();
 taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(88), .KEEP_W(8)) m_axis_cq();
@@ -39,6 +44,9 @@ taxi_axis_if #(.DATA_W(256), .USER_EN(1), .USER_W(75), .KEEP_W(8)) m_axis_rc();
 taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_rd_if();
 taxi_dma_ram_if #(.SEGS(4)) dma_ram_pcie_wr_if();
 
+taxi_apb_if #(.ADDR_W(pcie_dma_regs_pkg::PCIE_DMA_REGS_MIN_ADDR_WIDTH)) pcie_dma_apb();
+
+
 `ifndef SIM
 IBUFDS_GTE4 m_ibufds (
     .CEB('0),
@@ -49,6 +57,11 @@ IBUFDS_GTE4 m_ibufds (
 );
 `endif
 
+pcie_top_regs u_pcie_top_regs (
+    .s_apb              (s_apb),
+    .m_apb_pcie_dma_regs(pcie_dma_apb)
+);
+
 taxi_pcie_us_axil_master u_taxi_pcie_us_axil_master (
     .clk                (clk_250),
     .rst                (rst_250),
@@ -96,7 +109,7 @@ pcie_dma_wrapper u_pcie_dma_wrapper (
     .wr_dma_mst         (dma_ram_pcie_wr_if),
     .rd_dma_mst         (dma_ram_pcie_rd_if),
 
-    .s_apb              (m_apb[0])
+    .s_apb              (pcie_dma_apb)
 );
 
 `ifndef SIM

src/pcie/regs/compile_regs.sh

@@ -1,2 +1,2 @@
 peakrdl regblock -t pcie_dma_regs pcie_dma_regs.rdl -o . --cpuif apb4-flat
-peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif apb4-flat
+peakrdl busdecoder -t pcie_top_regs pcie_dma_regs.rdl pcie_top_regs.rdl -o . --cpuif taxi-apb

src/pcie/regs/pcie_top_regs.sv

@@ -11,30 +11,8 @@
 
 
 module pcie_top_regs (
-    input  logic s_apb_PCLK,
-    input  logic s_apb_PRESETn,
-    input  logic s_apb_PSEL,
-    input  logic s_apb_PENABLE,
-    input  logic s_apb_PWRITE,
-    input  logic [5:0] s_apb_PADDR,
-    input  logic [2:0] s_apb_PPROT,
-    input  logic [31:0] s_apb_PWDATA,
-    input  logic [3:0] s_apb_PSTRB,
-    output logic [31:0] s_apb_PRDATA,
-    output logic s_apb_PREADY,
-    output logic s_apb_PSLVERR,
-    output logic m_apb_pcie_dma_regs_PCLK,
-    output logic m_apb_pcie_dma_regs_PRESETn,
-    output logic m_apb_pcie_dma_regs_PSEL,
-    output logic m_apb_pcie_dma_regs_PENABLE,
-    output logic m_apb_pcie_dma_regs_PWRITE,
-    output logic [5:0] m_apb_pcie_dma_regs_PADDR,
-    output logic [2:0] m_apb_pcie_dma_regs_PPROT,
-    output logic [31:0] m_apb_pcie_dma_regs_PWDATA,
-    output logic [3:0] m_apb_pcie_dma_regs_PSTRB,
-    input  logic [31:0] m_apb_pcie_dma_regs_PRDATA,
-    input  logic m_apb_pcie_dma_regs_PREADY,
-    input  logic m_apb_pcie_dma_regs_PSLVERR
+    taxi_apb_if.slv s_apb,
+    taxi_apb_if.mst m_apb_pcie_dma_regs
 );
     //--------------------------------------------------------------------------
     // CPU Bus interface logic
@@ -68,31 +46,48 @@ module pcie_top_regs (
     // Slave <-> Internal CPUIF <-> Master
     //--------------------------------------------------------------------------
     
+    `ifndef SYNTHESIS
+        initial begin
+            assert_bad_addr_width: assert($bits(s_apb.paddr) >= pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH)
+                else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), pcie_top_regs_pkg::PCIE_TOP_REGS_MIN_ADDR_WIDTH);
+            assert_bad_data_width: assert($bits(s_apb.pwdata) == pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH)
+                else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), pcie_top_regs_pkg::PCIE_TOP_REGS_DATA_WIDTH);
+        end
+        `ifdef PEAKRDL_ASSERTIONS
+        assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
+            else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
+    `endif
 
-    assign cpuif_req   = s_apb_PSEL;
-    assign cpuif_wr_en = s_apb_PWRITE;
-    assign cpuif_rd_en = !s_apb_PWRITE;
+    assign cpuif_req   = s_apb.psel;
+    assign cpuif_wr_en = s_apb.pwrite;
+    assign cpuif_rd_en = !s_apb.pwrite;
 
-    assign cpuif_wr_addr = s_apb_PADDR;
-    assign cpuif_rd_addr = s_apb_PADDR;
+    assign cpuif_wr_addr = s_apb.paddr;
+    assign cpuif_rd_addr = s_apb.paddr;
 
-    assign cpuif_wr_data = s_apb_PWDATA;
-    assign cpuif_wr_byte_en = s_apb_PSTRB;
+    assign cpuif_wr_data = s_apb.pwdata;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
 
-    assign s_apb_PRDATA = cpuif_rd_data;
-    assign s_apb_PREADY = cpuif_rd_ack;
-    assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+    assign s_apb.prdata = cpuif_rd_data;
+    assign s_apb.pready = cpuif_rd_ack;
+    assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
 
     //--------------------------------------------------------------------------
     // Fanout CPU Bus interface signals
     //--------------------------------------------------------------------------
-    assign m_apb_pcie_dma_regs_PSEL = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
-    assign m_apb_pcie_dma_regs_PENABLE = s_apb_PENABLE;
-    assign m_apb_pcie_dma_regs_PWRITE = cpuif_wr_sel.pcie_dma_regs;
-    assign m_apb_pcie_dma_regs_PADDR = s_apb_PADDR[5:0];
-    assign m_apb_pcie_dma_regs_PPROT = s_apb_PPROT;
-    assign m_apb_pcie_dma_regs_PWDATA = cpuif_wr_data;
-    assign m_apb_pcie_dma_regs_PSTRB = cpuif_wr_byte_en;
+    assign m_apb_pcie_dma_regs.psel = cpuif_wr_sel.pcie_dma_regs|cpuif_rd_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.penable = s_apb.penable;
+    assign m_apb_pcie_dma_regs.pwrite = cpuif_wr_sel.pcie_dma_regs;
+    assign m_apb_pcie_dma_regs.paddr = s_apb.paddr;
+    assign m_apb_pcie_dma_regs.pprot = s_apb.pprot;
+    assign m_apb_pcie_dma_regs.pwdata = cpuif_wr_data;
+    assign m_apb_pcie_dma_regs.pstrb = cpuif_wr_byte_en;
+
+    //--------------------------------------------------------------------------
+    // Intermediate signals for interface array fanin
+    //--------------------------------------------------------------------------
+
 
     //--------------------------------------------------------------------------
     // Fanin CPU Bus interface signals
@@ -102,11 +97,11 @@ module pcie_top_regs (
         cpuif_rd_err = '0;
         cpuif_rd_data = '0;
         if (cpuif_rd_sel.pcie_dma_regs || cpuif_wr_sel.pcie_dma_regs) begin
-            cpuif_rd_ack = m_apb_pcie_dma_regs_PREADY;
-            cpuif_rd_err = m_apb_pcie_dma_regs_PSLVERR;
+            cpuif_rd_ack = m_apb_pcie_dma_regs.pready;
+            cpuif_rd_err = m_apb_pcie_dma_regs.pslverr;
         end
         if (cpuif_rd_sel.pcie_dma_regs) begin
-            cpuif_rd_data = m_apb_pcie_dma_regs_PRDATA;
+            cpuif_rd_data = m_apb_pcie_dma_regs.prdata;
         end
     end
 

src/pcie/sources.list

@@ -0,0 +1,9 @@
+regs/verilator.vlt
+
+regs/pcie_dma_regs_pkg.sv
+regs/pcie_dma_regs.sv
+regs/pcie_top_regs_pkg.sv
+regs/pcie_top_regs.sv
+
+pcie_dma_wrapper.sv
+pcie_top.sv

src/regs/alibaba_pcie_top_regs.py

@@ -0,0 +1,165 @@
+class AddrNode():
+    addr: int
+class alibaba_pcie_top_regsClass(AddrNode):
+    class pcie_top_regsClass(AddrNode):
+        class pcie_dma_regsClass(AddrNode):
+            class dma_rdClass(AddrNode):
+                class src_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
+                    self.src_addr_high = self.src_addr_highClass(self.addr + 4)
+                    self.dst_addr = self.dst_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            class dma_wrClass(AddrNode):
+                class dst_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
+                    self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
+                    self.src_addr = self.src_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.dma_rd = self.dma_rdClass(self.addr + 0)
+                self.dma_wr = self.dma_wrClass(self.addr + 32)
+        def __init__(self, addr: int = 0):
+            self.addr = addr
+            self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 0)
+    class eth_dma_wrapper_regsClass(AddrNode):
+        class eth_mac_25g_us_regsClass(AddrNode):
+            class commonClass(AddrNode):
+                class xcvr_gtpowergood_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class xcvr_qpll0lock_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class xcvr_qpll1lock_outClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.xcvr_gtpowergood_out = self.xcvr_gtpowergood_outClass(self.addr + 0)
+                    self.xcvr_qpll0lock_out = self.xcvr_qpll0lock_outClass(self.addr + 4)
+                    self.xcvr_qpll1lock_out = self.xcvr_qpll1lock_outClass(self.addr + 8)
+            class lanesClass(AddrNode):
+                class rx_block_lockClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class rx_statusClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.rx_block_lock = self.rx_block_lockClass(self.addr + 0)
+                    self.rx_status = self.rx_statusClass(self.addr + 4)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.common = self.commonClass(self.addr + 0)
+                self.lanes = [self.lanesClass(self.addr + 32 + 8*i) for i in range(2)]
+        class pcie_dma_regsClass(AddrNode):
+            class dma_rdClass(AddrNode):
+                class src_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.src_addr_low = self.src_addr_lowClass(self.addr + 0)
+                    self.src_addr_high = self.src_addr_highClass(self.addr + 4)
+                    self.dst_addr = self.dst_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            class dma_wrClass(AddrNode):
+                class dst_addr_lowClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class dst_addr_highClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class src_addrClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class lengthClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class triggerClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                class doneClass(AddrNode):
+                    def __init__(self, addr: int = 0):
+                        self.addr = addr
+                def __init__(self, addr: int = 0):
+                    self.addr = addr
+                    self.dst_addr_low = self.dst_addr_lowClass(self.addr + 0)
+                    self.dst_addr_high = self.dst_addr_highClass(self.addr + 4)
+                    self.src_addr = self.src_addrClass(self.addr + 8)
+                    self.length = self.lengthClass(self.addr + 12)
+                    self.trigger = self.triggerClass(self.addr + 16)
+                    self.done = self.doneClass(self.addr + 20)
+            def __init__(self, addr: int = 0):
+                self.addr = addr
+                self.dma_rd = self.dma_rdClass(self.addr + 0)
+                self.dma_wr = self.dma_wrClass(self.addr + 32)
+        def __init__(self, addr: int = 0):
+            self.addr = addr
+            self.eth_mac_25g_us_regs = self.eth_mac_25g_us_regsClass(self.addr + 0)
+            self.pcie_dma_regs = self.pcie_dma_regsClass(self.addr + 128)
+    def __init__(self, addr: int = 0):
+        self.addr = addr
+        self.pcie_top_regs = self.pcie_top_regsClass(self.addr + 0)
+        self.eth_dma_wrapper_regs = self.eth_dma_wrapper_regsClass(self.addr + 256)

src/regs/alibaba_pcie_top_regs.sv

@@ -3,50 +3,17 @@
 //  Description: CPU Interface Bus Decoder
 //  Author: PeakRDL-BusDecoder
 //  License: LGPL-3.0
-//  Date: 2025-11-22
-//  Version: 0.5.0
+//  Date: 2025-11-23
+//  Version: 0.6.0
 //  Links:
 //    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
 //==========================================================
 
 
 module alibaba_pcie_top_regs (
-    input  logic s_apb_PCLK,
-    input  logic s_apb_PRESETn,
-    input  logic s_apb_PSEL,
-    input  logic s_apb_PENABLE,
-    input  logic s_apb_PWRITE,
-    input  logic [8:0] s_apb_PADDR,
-    input  logic [2:0] s_apb_PPROT,
-    input  logic [31:0] s_apb_PWDATA,
-    input  logic [3:0] s_apb_PSTRB,
-    output logic [31:0] s_apb_PRDATA,
-    output logic s_apb_PREADY,
-    output logic s_apb_PSLVERR,
-    output logic m_apb_pcie_top_regs_PCLK,
-    output logic m_apb_pcie_top_regs_PRESETn,
-    output logic m_apb_pcie_top_regs_PSEL,
-    output logic m_apb_pcie_top_regs_PENABLE,
-    output logic m_apb_pcie_top_regs_PWRITE,
-    output logic [5:0] m_apb_pcie_top_regs_PADDR,
-    output logic [2:0] m_apb_pcie_top_regs_PPROT,
-    output logic [31:0] m_apb_pcie_top_regs_PWDATA,
-    output logic [3:0] m_apb_pcie_top_regs_PSTRB,
-    input  logic [31:0] m_apb_pcie_top_regs_PRDATA,
-    input  logic m_apb_pcie_top_regs_PREADY,
-    input  logic m_apb_pcie_top_regs_PSLVERR,
-    output logic m_apb_eth_dma_wrapper_regs_PCLK,
-    output logic m_apb_eth_dma_wrapper_regs_PRESETn,
-    output logic m_apb_eth_dma_wrapper_regs_PSEL,
-    output logic m_apb_eth_dma_wrapper_regs_PENABLE,
-    output logic m_apb_eth_dma_wrapper_regs_PWRITE,
-    output logic [7:0] m_apb_eth_dma_wrapper_regs_PADDR,
-    output logic [2:0] m_apb_eth_dma_wrapper_regs_PPROT,
-    output logic [31:0] m_apb_eth_dma_wrapper_regs_PWDATA,
-    output logic [3:0] m_apb_eth_dma_wrapper_regs_PSTRB,
-    input  logic [31:0] m_apb_eth_dma_wrapper_regs_PRDATA,
-    input  logic m_apb_eth_dma_wrapper_regs_PREADY,
-    input  logic m_apb_eth_dma_wrapper_regs_PSLVERR
+    taxi_apb_if.slv s_apb,
+    taxi_apb_if.mst m_apb_pcie_top_regs,
+    taxi_apb_if.mst m_apb_eth_dma_wrapper_regs
 );
     //--------------------------------------------------------------------------
     // CPU Bus interface logic
@@ -81,38 +48,55 @@ module alibaba_pcie_top_regs (
     // Slave <-> Internal CPUIF <-> Master
     //--------------------------------------------------------------------------
     
+    `ifndef SYNTHESIS
+        initial begin
+            assert_bad_addr_width: assert($bits(s_apb.paddr) >= alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH)
+                else $error("Interface address width of %0d is too small. Shall be at least %0d bits", $bits(s_apb.paddr), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_MIN_ADDR_WIDTH);
+            assert_bad_data_width: assert($bits(s_apb.pwdata) == alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH)
+                else $error("Interface data width of %0d is incorrect. Shall be %0d bits", $bits(s_apb.pwdata), alibaba_pcie_top_regs_pkg::ALIBABA_PCIE_TOP_REGS_DATA_WIDTH);
+        end
+        `ifdef PEAKRDL_ASSERTIONS
+        assert_wr_sel: assert property (@(posedge s_apb.PCLK) s_apb.psel && s_apb.pwrite |-> ##1 (s_apb.pready || s_apb.pslverr))
+            else $error("APB4 Slave port SEL implies that cpuif_wr_sel must be one-hot encoded");
+        `endif
+    `endif
 
-    assign cpuif_req   = s_apb_PSEL;
-    assign cpuif_wr_en = s_apb_PWRITE;
-    assign cpuif_rd_en = !s_apb_PWRITE;
+    assign cpuif_req   = s_apb.psel;
+    assign cpuif_wr_en = s_apb.pwrite;
+    assign cpuif_rd_en = !s_apb.pwrite;
 
-    assign cpuif_wr_addr = s_apb_PADDR;
-    assign cpuif_rd_addr = s_apb_PADDR;
+    assign cpuif_wr_addr = s_apb.paddr;
+    assign cpuif_rd_addr = s_apb.paddr;
 
-    assign cpuif_wr_data = s_apb_PWDATA;
-    assign cpuif_wr_byte_en = s_apb_PSTRB;
+    assign cpuif_wr_data = s_apb.pwdata;
+    assign cpuif_wr_byte_en = s_apb.pstrb;
 
-    assign s_apb_PRDATA = cpuif_rd_data;
-    assign s_apb_PREADY = cpuif_rd_ack;
-    assign s_apb_PSLVERR = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
+    assign s_apb.prdata = cpuif_rd_data;
+    assign s_apb.pready = cpuif_rd_ack;
+    assign s_apb.pslverr = cpuif_rd_err | cpuif_rd_sel.cpuif_err | cpuif_wr_sel.cpuif_err;
 
     //--------------------------------------------------------------------------
     // Fanout CPU Bus interface signals
     //--------------------------------------------------------------------------
-    assign m_apb_pcie_top_regs_PSEL = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
-    assign m_apb_pcie_top_regs_PENABLE = s_apb_PENABLE;
-    assign m_apb_pcie_top_regs_PWRITE = cpuif_wr_sel.pcie_top_regs;
-    assign m_apb_pcie_top_regs_PADDR = s_apb_PADDR[5:0];
-    assign m_apb_pcie_top_regs_PPROT = s_apb_PPROT;
-    assign m_apb_pcie_top_regs_PWDATA = cpuif_wr_data;
-    assign m_apb_pcie_top_regs_PSTRB = cpuif_wr_byte_en;
-    assign m_apb_eth_dma_wrapper_regs_PSEL = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
-    assign m_apb_eth_dma_wrapper_regs_PENABLE = s_apb_PENABLE;
-    assign m_apb_eth_dma_wrapper_regs_PWRITE = cpuif_wr_sel.eth_dma_wrapper_regs;
-    assign m_apb_eth_dma_wrapper_regs_PADDR = s_apb_PADDR[7:0];
-    assign m_apb_eth_dma_wrapper_regs_PPROT = s_apb_PPROT;
-    assign m_apb_eth_dma_wrapper_regs_PWDATA = cpuif_wr_data;
-    assign m_apb_eth_dma_wrapper_regs_PSTRB = cpuif_wr_byte_en;
+    assign m_apb_pcie_top_regs.psel = cpuif_wr_sel.pcie_top_regs|cpuif_rd_sel.pcie_top_regs;
+    assign m_apb_pcie_top_regs.penable = s_apb.penable;
+    assign m_apb_pcie_top_regs.pwrite = cpuif_wr_sel.pcie_top_regs;
+    assign m_apb_pcie_top_regs.paddr = s_apb.paddr;
+    assign m_apb_pcie_top_regs.pprot = s_apb.pprot;
+    assign m_apb_pcie_top_regs.pwdata = cpuif_wr_data;
+    assign m_apb_pcie_top_regs.pstrb = cpuif_wr_byte_en;
+    assign m_apb_eth_dma_wrapper_regs.psel = cpuif_wr_sel.eth_dma_wrapper_regs|cpuif_rd_sel.eth_dma_wrapper_regs;
+    assign m_apb_eth_dma_wrapper_regs.penable = s_apb.penable;
+    assign m_apb_eth_dma_wrapper_regs.pwrite = cpuif_wr_sel.eth_dma_wrapper_regs;
+    assign m_apb_eth_dma_wrapper_regs.paddr = s_apb.paddr;
+    assign m_apb_eth_dma_wrapper_regs.pprot = s_apb.pprot;
+    assign m_apb_eth_dma_wrapper_regs.pwdata = cpuif_wr_data;
+    assign m_apb_eth_dma_wrapper_regs.pstrb = cpuif_wr_byte_en;
+
+    //--------------------------------------------------------------------------
+    // Intermediate signals for interface array fanin
+    //--------------------------------------------------------------------------
+
 
     //--------------------------------------------------------------------------
     // Fanin CPU Bus interface signals
@@ -122,18 +106,18 @@ module alibaba_pcie_top_regs (
         cpuif_rd_err = '0;
         cpuif_rd_data = '0;
         if (cpuif_rd_sel.pcie_top_regs || cpuif_wr_sel.pcie_top_regs) begin
-            cpuif_rd_ack = m_apb_pcie_top_regs_PREADY;
-            cpuif_rd_err = m_apb_pcie_top_regs_PSLVERR;
+            cpuif_rd_ack = m_apb_pcie_top_regs.pready;
+            cpuif_rd_err = m_apb_pcie_top_regs.pslverr;
         end
         if (cpuif_rd_sel.pcie_top_regs) begin
-            cpuif_rd_data = m_apb_pcie_top_regs_PRDATA;
+            cpuif_rd_data = m_apb_pcie_top_regs.prdata;
         end
         if (cpuif_rd_sel.eth_dma_wrapper_regs || cpuif_wr_sel.eth_dma_wrapper_regs) begin
-            cpuif_rd_ack = m_apb_eth_dma_wrapper_regs_PREADY;
-            cpuif_rd_err = m_apb_eth_dma_wrapper_regs_PSLVERR;
+            cpuif_rd_ack = m_apb_eth_dma_wrapper_regs.pready;
+            cpuif_rd_err = m_apb_eth_dma_wrapper_regs.pslverr;
         end
         if (cpuif_rd_sel.eth_dma_wrapper_regs) begin
-            cpuif_rd_data = m_apb_eth_dma_wrapper_regs_PRDATA;
+            cpuif_rd_data = m_apb_eth_dma_wrapper_regs.prdata;
         end
     end
 

src/regs/alibaba_pcie_top_regs_pkg.sv

@@ -3,8 +3,8 @@
 //  Description: CPU Interface Bus Decoder Package
 //  Author: PeakRDL-BusDecoder
 //  License: LGPL-3.0
-//  Date: 2025-11-22
-//  Version: 0.5.0
+//  Date: 2025-11-23
+//  Version: 0.6.0
 //  Links:
 //    - https://github.com/arnavsacheti/PeakRDL-BusDecoder
 //==========================================================

src/regs/compile_regs.sh

@@ -1,4 +1,6 @@
 SRCS="../pcie/regs/pcie_dma_regs.rdl ../pcie/regs/pcie_top_regs.rdl ../eth/regs/eth_mac_25g_us_regs.rdl ../eth/regs/eth_dma_wrapper_regs.rdl alibaba_pcie_top.rdl"
 
-peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif apb4-flat
+peakrdl busdecoder -t alibaba_pcie_top_regs $SRCS -o . --cpuif taxi-apb
+peakrdl python-regmap -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.py
+peakrdl html -t alibaba_pcie_top_regs $SRCS -o html
 peakrdl c-header -t alibaba_pcie_top_regs $SRCS -o alibaba_pcie_top_regs.h

src/regs/verilator.vlt

@@ -0,0 +1,4 @@
+`verilator_config
+
+lint_off -rule MULTIDRIVEN -file "**/regs/*"
+lint_off -file "**/regs/*"

sw/test/alibaba_pcie_top_regs.h

@@ -0,0 +1 @@
+../../src/regs/alibaba_pcie_top_regs.h

sw/test/pcie_dma_test.c

@@ -7,6 +7,8 @@
 #include <sys/mman.h>
 #include <string.h>
 
+#include "alibaba_pcie_top_regs.h"
+
 typedef struct {
     uint64_t pfn : 55;
     unsigned int soft_dirty : 1;
@@ -105,8 +107,8 @@ int main(void)
     // this is hardcoded, seems to be deterministic.
     uint32_t pcie_physical_base_offset = 0xfe800000;
     int fd = open("/dev/mem", O_RDWR|O_SYNC);
-    uint32_t* pcie_base = (uint32_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
-    printf("Virtual PCIe Base: %p\n", pcie_base);
+    alibaba_pcie_top_regs_t* top_regs = (alibaba_pcie_top_regs_t*)mmap(0, 64, PROT_READ|PROT_WRITE, MAP_SHARED, fd, pcie_physical_base_offset);
+    printf("Virtual PCIe Base: %p\n", top_regs);
 
 
     for (int i = 0; i < 2; i++) { 
@@ -119,34 +121,60 @@ int main(void)
         memset((void*)dst, 0, 1024);
 
         printf("Sending read DMA\n");
-        pcie_base[0] = (uint32_t)src_phys;
-        pcie_base[1] = (uint32_t)(src_phys >> 32);
-        pcie_base[2] = dma_mem_addr;
-        pcie_base[3] = strlen(src);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_low = (uint32_t)src_phys;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_high = (uint32_t)(src_phys >> 32);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.dst_addr = dma_mem_addr;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.length = strlen(src);
 
         for (int i = 0; i < 4; i++) {
-            printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
+            printf("pcie_rd_dma[%d] = %x\n", i, (&top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.src_addr_low)[i]);
         }
 
-        pcie_base[4] = 1;
-        printf("%d\n", pcie_base[4]);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.trigger = 1;
+        printf("%d\n", top_regs->pcie_top_regs.pcie_dma_regs.dma_rd.trigger);
         printf("\n\n");
 
         printf("Sending write DMA\n");
 
+        // we use dma_mem_addr twice, but these are actually 2 separate memories.
 
-        printf("Sending read DMA\n");
-        pcie_base[8] = (uint32_t)dst_phys;
-        pcie_base[9] = (uint32_t)(dst_phys >> 32);
-        pcie_base[10] = dma_mem_addr;
-        pcie_base[11] = strlen(src);
+        // Set up stream to memory DMA to store ethernet frame
+        printf("Setting up stream to memory DMA\n");
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.src_addr = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_low = dma_mem_addr;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_high =  0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.length = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.trigger = 1;
 
-        for (int i = 8; i < 12; i++) {
-            printf("pcie_base[%d] = %x\n", i, pcie_base[i]);
+        for (int i = 0; i < 4; i++) {
+            printf("eth_wr_dma[%d] = %x\n", i, (&top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_wr.dst_addr_low )[i]);
         }
 
-        pcie_base[12] = 1;
-        printf("%d\n", pcie_base[12]);
+        // Trigger memory to stream dma to send ethernet frame
+        printf("Sending memory to stream DMA\n");
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_low = dma_mem_addr;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_high = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.dst_addr = 0;
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.length = strlen(src);
+        top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.trigger = 1;
+
+        for (int i = 0; i < 4; i++) {
+            printf("eth_rd_dma[%d] = %x\n", i, (&top_regs->eth_dma_wrapper_regs.pcie_dma_regs.dma_rd.src_addr_low)[i]);
+        }
+
+
+        printf("Sending read DMA\n");
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_low = (uint32_t)dst_phys;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_high = (uint32_t)(dst_phys >> 32);
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.src_addr = dma_mem_addr;
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.length = strlen(src);
+
+        for (int i = 8; i < 12; i++) {
+            printf("pcie_wr_dma[%d] = %x\n", i, (&top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.dst_addr_low)[i]);
+        }
+
+        top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.trigger = 1;
+        printf("%d\n", top_regs->pcie_top_regs.pcie_dma_regs.dma_wr.trigger);
         printf("\n\n");
 
         printf("strlen(dst)=%d\n", strlen(dst));