Wrap access on RAM size
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@@ -31,7 +31,7 @@ class AxiRamWrite(AxiSlaveWrite, Memory):
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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async def _write(self, address, data):
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async def _write(self, address, data):
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self.write(address, data)
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self.write(address % self.size, data)
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class AxiRamRead(AxiSlaveRead, Memory):
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class AxiRamRead(AxiSlaveRead, Memory):
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@@ -39,7 +39,7 @@ class AxiRamRead(AxiSlaveRead, Memory):
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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async def _read(self, address, length):
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async def _read(self, address, length):
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return self.read(address, length)
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return self.read(address % self.size, length)
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class AxiRam(Memory):
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class AxiRam(Memory):
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@@ -31,7 +31,7 @@ class AxiLiteRamWrite(AxiLiteSlaveWrite, Memory):
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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async def _write(self, address, data):
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async def _write(self, address, data):
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self.write(address, data)
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self.write(address % self.size, data)
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class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
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class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
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@@ -39,7 +39,7 @@ class AxiLiteRamRead(AxiLiteSlaveRead, Memory):
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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super().__init__(bus, clock, reset, reset_active_level=reset_active_level, size=size, mem=mem, **kwargs)
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async def _read(self, address, length):
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async def _read(self, address, length):
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return self.read(address, length)
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return self.read(address % self.size, length)
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class AxiLiteRam(Memory):
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class AxiLiteRam(Memory):
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