Change target clock to 400MHz

2025-07-02 10:08:25 -07:00
parent 548bee1144
commit 2b8286d180
3 changed files with 10 additions and 5 deletions
--- a/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc
+++ b/ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc
@@ -1 +1 @@
-create_clock -period 4.0 -name clk [get_ports i_clk]
+create_clock -period 2.5 -name clk [get_ports i_clk]