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Change target clock to 400MHz

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Byron Lathi
2025-07-02 10:08:25 -07:00
parent 548bee1144
commit 2b8286d180
3 changed files with 10 additions and 5 deletions
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7
ChaCha20_Poly1305_64/chacha20_timing_test/chacha20_timing_test.xml
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@@ -1,14 +1,15 @@
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<efx:project name="chacha20_timing_test" description="" last_change="1751223371" sw_version="2025.1.110" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd"> <efx:project name="chacha20_timing_test" description="" last_change="1751475390" sw_version="2025.1.110" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="true" design_ood="sync" place_ood="sync" route_ood="sync" xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">
<efx:device_info> <efx:device_info>
<efx:family name="Titanium"/> <efx:family name="Titanium"/>
<efx:device name="Ti375N1156"/> <efx:device name="Ti375N1156"/>
<efx:timing_model name="C4"/> <efx:timing_model name="C4"/>
</efx:device_info> </efx:device_info>
<efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008" unified_flow="false"> <efx:design_info def_veri_version="sv_09" def_vhdl_version="vhdl_2008" unified_flow="false">
<efx:top_module name="chacha20_block"/> <efx:top_module name="chacha20_pipelined_block"/>
<efx:design_file name="../src/chacha20_pipelined_block.sv" version="default" library="default"/>
<efx:design_file name="../src/chacha20_pipelined_round.sv" version="default" library="default"/>
<efx:design_file name="../src/chacha20_qr.sv" version="default" library="default"/> <efx:design_file name="../src/chacha20_qr.sv" version="default" library="default"/>
<efx:design_file name="../src/chacha20_block.sv" version="default" library="default"/>
<efx:top_vhdl_arch name=""/> <efx:top_vhdl_arch name=""/>
</efx:design_info> </efx:design_info>
<efx:constraint_info> <efx:constraint_info>

2
ChaCha20_Poly1305_64/chacha20_timing_test/constraints.sdc
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@@ -1 +1 @@
create_clock -period 4.0 -name clk [get_ports i_clk] create_clock -period 2.5 -name clk [get_ports i_clk]

6
ChaCha20_Poly1305_64/doc/notes.md
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@@ -101,4 +101,8 @@ Lets just leave it for now even if its overkill. The hardware would support up t
we designed a custom board for it (or 120 if we used FMC connectors). we designed a custom board for it (or 120 if we used FMC connectors).
If we only use a single quarter round multiplexed between all 4, then the same If we only use a single quarter round multiplexed between all 4, then the same
quarter round module can have 2 different blocks going through it at once. quarter round module can have 2 different blocks going through it at once.
The new one multiplexes 4 quarter rounds between 1 QR module which reduces the
logic usage down to only 46k le, of which the vast majority is flops (2k ff per round,
0.5k lut)