Byron Lathi
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2fd1136154
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Actually randomize testing
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2025-10-27 20:13:21 -07:00 |
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Byron Lathi
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06d5949aa7
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Add rtl for friendly_modulo
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2025-10-27 19:19:43 -07:00 |
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Byron Lathi
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003527ee0d
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Do poly1305 with absolutely no modulo operators
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2025-10-26 16:09:16 -07:00 |
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Byron Lathi
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fd50ecc4f0
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Calculate r powers ahead of time
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2025-10-26 15:43:58 -07:00 |
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Byron Lathi
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faef39c4d3
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Add modulo theory
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2025-10-26 15:43:36 -07:00 |
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Byron Lathi
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5e3b7be854
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Add parallel implementation
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2025-10-24 18:46:30 -07:00 |
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Byron Lathi
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d9651e9074
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Add poly1305 python implementation
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2025-10-24 08:25:35 -07:00 |
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Byron Lathi
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80e3faeae6
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ramblings
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2025-07-14 11:10:43 -07:00 |
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Byron Lathi
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2b57079205
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Add poly1305 and synthesis test
Wow this does not come even close to passing timing. Need to be smarter
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2025-07-05 07:30:18 -07:00 |
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Byron Lathi
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7f91a8af32
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Get poly1305 core to kind of work
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2025-07-04 10:49:48 -07:00 |
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Byron Lathi
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2b8286d180
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Change target clock to 400MHz
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2025-07-02 10:08:34 -07:00 |
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Byron Lathi
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2afe869dee
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Add missing ready, fix constant endianness
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2025-07-02 09:39:55 -07:00 |
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Byron Lathi
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a617277005
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First shot at 1/4 version
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2025-07-02 06:32:58 -07:00 |
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Byron Lathi
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196ea8e6d3
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Add correct amount of memory
should be 160, not 20. There are 8 cycles per stage and 20 stages
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2025-06-29 13:29:38 -07:00 |
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Byron Lathi
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4c7badbbbb
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Change target frequency to 250
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2025-06-28 21:15:01 -07:00 |
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Byron Lathi
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20d98e117b
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Get sim working, make some changes to the final addition
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2025-06-28 20:34:46 -07:00 |
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Byron Lathi
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8136a7526b
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Add basic repo
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2025-06-28 15:48:14 -07:00 |
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Byron Lathi
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369e29557c
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add notes
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2025-06-23 00:02:14 -07:00 |
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