Byron Lathi
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196ea8e6d3
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Add correct amount of memory
should be 160, not 20. There are 8 cycles per stage and 20 stages
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2025-06-29 13:29:38 -07:00 |
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Byron Lathi
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4c7badbbbb
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Change target frequency to 250
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2025-06-28 21:15:01 -07:00 |
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Byron Lathi
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20d98e117b
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Get sim working, make some changes to the final addition
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2025-06-28 20:34:46 -07:00 |
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Byron Lathi
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8136a7526b
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Add basic repo
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2025-06-28 15:48:14 -07:00 |
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Byron Lathi
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369e29557c
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add notes
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2025-06-23 00:02:14 -07:00 |
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Byron Lathi
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4b67e7aa5a
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Initial Commit
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2025-06-22 21:43:49 -07:00 |
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