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Revert FST, use VCD instead
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Byron Lathi
2026-02-07 15:45:27 -08:00
parent 2df2a5554c
commit 069e87decf
2 changed files with 3 additions and 3 deletions
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2
pyproject.toml
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@@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami
# https://packaging.python.org/guides/single-sourcing-package-version/ # https://packaging.python.org/guides/single-sourcing-package-version/
# dynamic = ["version"] # dynamic = ["version"]
version = "0.5.2" # REQUIRED, although can be dynamic version = "0.5.3" # REQUIRED, although can be dynamic
# This is a one-line description or tagline of what your project does. This # This is a one-line description or tagline of what your project does. This
# corresponds to the "Summary" metadata field: # corresponds to the "Summary" metadata field:

4
src/fpga_sim/fpga_sim.py
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@@ -107,8 +107,8 @@ def fpga_sim_main():
build_args = ["--timing"] build_args = ["--timing"]
# By default, verilator only uses vcd instead of fst, but fst is better. # By default, verilator only uses vcd instead of fst, but fst is better.
if test["waves"]: #if test["waves"]:
build_args.append("--trace-fst") # build_args.append("--trace-fst")
try: try:
runner.build( runner.build(