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fpga-sim
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Byron Lathi
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Set language type to verilog
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hate vhdl
2025-11-22 16:56:02 -08:00
.gitea
/workflows
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2025-11-08 14:33:28 -08:00
src
/fpga_sim
Set language type to verilog
2025-11-22 16:56:02 -08:00
.gitignore
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2024-11-29 22:31:03 -08:00
.gitlab-ci.yml
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init_env.sh
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LICENSE.txt
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pyproject.toml
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README.md
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requirements.txt
Experimental/incdirs
2025-03-21 05:45:28 +00:00
README.md
FPGA Sim
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Python
98%
Shell
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