bslathi19/fpga-sim
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
32 Commits 6 Branches 1 Tag

Default Branch

master
All checks were successful
Publish Package / Build Package (push) Successful in 2m38s
Details
Publish Package / Deploy Package (push) Successful in 42s
Details

a4e512e5f9 · Update version · Updated 2026-08-12 20:23:51 -07:00
 ZIP  TAR.GZ

Branches

dev/trace_fst
All checks were successful
Publish Package / Build Package (push) Successful in 7s
Details
Publish Package / Deploy Package (push) Successful in 9s
Details

2d3d02eee9 · Try 2 · Updated 2025-11-09 14:00:53 -08:00    bslathi19

9
0
 #1 Merged
 ZIP  TAR.GZ
filter_verilog

983e3f76f3 · Add timing option · Updated 2025-07-16 22:28:36 -07:00    bslathi19

14
1
 ZIP  TAR.GZ
exp/filter_verilog

59b77618b0 · Add VERILATOR define by default · Updated 2025-03-29 19:37:11 -07:00    bslathi19

17
5
 ZIP  TAR.GZ
experimental/incdirs

77e0269800 · Filter out only verilog sources (and verilator lint files) · Updated 2025-03-29 19:28:30 -07:00    bslathi19

17
4
 ZIP  TAR.GZ
quote_compat

b3defd3474 · Fix quotes for old python compatibility · Updated 2025-02-08 14:59:32 -08:00    bslathi19

19
0
 Included
 ZIP  TAR.GZ