Revert FST, use VCD instead

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.5.2"  # REQUIRED, although can be dynamic
+version = "0.5.3"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -107,8 +107,8 @@ def fpga_sim_main():
         build_args = ["--timing"]
 
         # By default, verilator only uses vcd instead of fst, but fst is better.
-        if test["waves"]:
-            build_args.append("--trace-fst")
+        #if test["waves"]:
+        #    build_args.append("--trace-fst")
 
         try:
             runner.build(