Set language type to verilog

hate vhdl

pyproject.toml

@@ -35,7 +35,7 @@ name = "fpga-sim"  # REQUIRED, is the only field that cannot be marked as dynami
 # https://packaging.python.org/guides/single-sourcing-package-version/
 
 # dynamic = ["version"]
-version = "0.5.1"  # REQUIRED, although can be dynamic
+version = "0.5.2"  # REQUIRED, although can be dynamic
 
 # This is a one-line description or tagline of what your project does. This
 # corresponds to the "Summary" metadata field:

src/fpga_sim/fpga_sim.py

@@ -128,5 +128,5 @@ def fpga_sim_main():
 
         sys.path.append(test["base_path"])
 
-        runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
+        runner.test(hdl_toplevel_lang="verilog", hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)