bslathi19/fpga-sim
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix base path issue

Browse Source
This commit is contained in:
Byron Lathi
2024-11-30 00:33:59 -08:00
parent b7a1f433c5
commit d63d3d3270
2 changed files with 3 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
pyproject.toml
View File

@@ -35,7 +35,7 @@ name = "fpga-sim" # REQUIRED, is the only field that cannot be marked as dynami
# https://packaging.python.org/guides/single-sourcing-package-version/ # https://packaging.python.org/guides/single-sourcing-package-version/
# dynamic = ["version"] # dynamic = ["version"]
version = "0.0.4" # REQUIRED, although can be dynamic version = "0.0.5" # REQUIRED, although can be dynamic
# This is a one-line description or tagline of what your project does. This # This is a one-line description or tagline of what your project does. This
# corresponds to the "Summary" metadata field: # corresponds to the "Summary" metadata field:

9
src/fpga_sim/fpga_sim.py
View File

@@ -32,7 +32,6 @@ def fpga_sim_main():
# 2: Figure out which tests to run # 2: Figure out which tests to run
base_path = os.path.split(os.path.abspath(args.yaml))[0] base_path = os.path.split(os.path.abspath(args.yaml))[0]
print(base_path)
tests = [] tests = []
@@ -41,11 +40,11 @@ def fpga_sim_main():
if test["type"] == "yaml": if test["type"] == "yaml":
with open(f"{_base_path}/{test["yaml"]}") as _cfg_file: with open(f"{_base_path}/{test["yaml"]}") as _cfg_file:
__cfg = yaml.safe_load(_cfg_file) __cfg = yaml.safe_load(_cfg_file)
parse_cfg(__cfg, f"{base_path}/{os.path.split(test["yaml"])[0]}") parse_cfg(__cfg, f"{_base_path}/{os.path.split(test["yaml"])[0]}")
if test["type"] == "test": if test["type"] == "test":
waves = test["waves"] if "waves" in test else None waves = test["waves"] if "waves" in test else None
tests.append({ tests.append({
"base_path": base_path, "base_path": _base_path,
"name": test["name"], "name": test["name"],
"toplevel": test["toplevel"], "toplevel": test["toplevel"],
"modules": test["modules"], "modules": test["modules"],
@@ -82,7 +81,3 @@ def fpga_sim_main():
sys.path.append(test["base_path"]) sys.path.append(test["base_path"])
runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml) runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
if __name__ == "__main__":
main()