110 lines
2.9 KiB
Python
110 lines
2.9 KiB
Python
from ast import parse
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from email.mime import base
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import os
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import sys
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import argparse
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from cocotb.runner import get_runner
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from rtl_manifest import rtl_manifest
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import yaml
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def fpga_sim_main():
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# 1: Parse Arguments.
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parser = argparse.ArgumentParser(
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prog="sim",
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description="Tool to simulate"
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)
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parser.add_argument("yaml")
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parser.add_argument("test_name", nargs="?")
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args = parser.parse_args()
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print(args.test_name)
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# print(args.yaml)
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with open(args.yaml) as cfg_file:
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cfg = yaml.safe_load(cfg_file)
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# 2: Figure out which tests to run
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base_path = os.path.split(os.path.abspath(args.yaml))[0]
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tests = []
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defines = {}
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def parse_cfg(_cfg, _base_path=None):
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if "yaml" in _cfg:
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for sub_yaml in _cfg["yaml"]:
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print(sub_yaml)
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with open(f"{_base_path}/{sub_yaml}") as _cfg_file:
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__cfg = yaml.safe_load(_cfg_file)
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print(f"Base Path: {_base_path}/{os.path.split(sub_yaml)[0]}")
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parse_cfg(__cfg, f"{_base_path}/{os.path.split(sub_yaml)[0]}")
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if "tests" in _cfg:
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for test in _cfg["tests"]:
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print(test)
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if "waves" not in test:
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waves = False
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else:
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waves = test["waves"]
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tests.append({
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"base_path": _base_path,
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"name": test["name"],
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"toplevel": test["toplevel"],
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"modules": test["modules"],
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"waves": waves,
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"sources": test["sources"]
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})
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if "defines" in _cfg:
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cfg_defines = _cfg["defines"]
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for define in cfg_defines:
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print(f"{define}: {cfg_defines[define]}, {os.path.expandvars(cfg_defines[define])}")
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defines[define] = os.path.expandvars(cfg_defines[define])
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parse_cfg(cfg, base_path)
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# 4: Run those tests
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sim = os.getenv("SIM", "verilator")
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runner = get_runner(sim)
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os.environ["MAKEFLAGS"] = "-j"
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tests_to_run = []
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if args.test_name is not None:
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for test in tests:
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if test["name"] == args.test_name:
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tests_to_run.append(test)
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else:
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tests_to_run = tests
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# Turn this into a multiprocessing pool
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for test in tests_to_run:
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sources = rtl_manifest.read_sources(f"{test['base_path']}/{test['sources']}")
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runner.build(
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verilog_sources=sources,
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hdl_toplevel=test["toplevel"],
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build_dir=f"{test["base_path"]}/sim_build",
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waves=test["waves"],
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defines=defines
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)
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result_xml = f"../sim_build/{test["name"]}_results.xml".replace(" ", "_")
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sys.path.append(test["base_path"])
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runner.test(hdl_toplevel=test["toplevel"], test_module=test["modules"], waves=test["waves"], results_xml=result_xml)
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