Add external memory

2026-04-18 18:40:30 -07:00
parent 756b96d9e2
commit 048af1c341
8 changed files with 168 additions and 14 deletions
--- a/sim/verilog6502_wrapper_tb.sv
+++ b/sim/verilog6502_wrapper_tb.sv
@@ -3,7 +3,7 @@ module verilog6502_wrapper_tb();
 `define SIM

 taxi_apb_if s_apb();
-taxi_axi_if m_axi();
+taxi_axil_if m_axil();
 taxi_axi_if s_axi();

 logic clk;
@@ -18,8 +18,8 @@ verilog6502_wrapper u_dut(
    .clk(clk),
    .rst(rst),
    .s_apb(s_apb),
-    .m_axi_rd(m_axi),
-    .m_axi_wr(m_axi),
+    .m_axil_rd(m_axil),
+    .m_axil_wr(m_axil),
    .s_axi_rd(s_axi),
    .s_axi_wr(s_axi),
    .o_irq_ext(o_irq_ext),