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Add external memory

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Byron Lathi
2026-04-18 18:40:30 -07:00
parent 756b96d9e2
commit 048af1c341
8 changed files with 168 additions and 14 deletions
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8
sim/verilog6502_wrapper_test.py
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@@ -5,7 +5,7 @@ from cocotb.clock import Clock
from cocotb.triggers import Timer, RisingEdge
from cocotbext.axi.apb import ApbMaster, ApbBus
from cocotbext.axi import AxiMaster, AxiBus
from cocotbext.axi import AxiMaster, AxiBus, AxiLiteBus, AxiLiteRam
@@ -20,6 +20,9 @@ async def test_sanity(dut):
s_apb = ApbMaster(ApbBus.from_prefix(dut.s_apb, ""), dut.clk, dut.rst)
s_axi = AxiMaster(AxiBus.from_prefix(dut.s_axi, ""), dut.clk, dut.rst)
m_axil = AxiLiteRam(AxiLiteBus.from_prefix(dut.m_axil, ""), dut.clk, dut.rst, size=2**32)
m_axil.write(0, b"Hello, world!")
dut.rst.value = Immediate(1)
@@ -29,7 +32,8 @@ async def test_sanity(dut):
for _ in range(10):
await RisingEdge(dut.clk)
await s_axi.write(0x200, [0x58, 0xa9, 0x00, 0x1a, 0xcb, 0x4c, 0x02, 0x03])
# await s_axi.write(0x200, [0x58, 0xa9, 0x00, 0x1a, 0xcb, 0x4c, 0x03, 0x02])
await s_axi.write(0x200, [0xAD, 0x00, 0xE0, 0xAD, 0x01, 0xE0, 0xAD, 0x02, 0xE0, 0xAD, 0x03, 0xE0, 0xAD, 0x04, 0xE0, 0xCB])
cocotb.start_soon(s_axi.read(0x200, 8))