30 lines
450 B
Systemverilog
30 lines
450 B
Systemverilog
module verilog6502_wrapper_tb();
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`define SIM
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taxi_apb_if s_apb();
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taxi_axil_if m_axil();
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taxi_axi_if s_axi();
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logic clk;
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logic rst;
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logic o_irq_ext;
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logic i_irq_ext;
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logic i_nmi_ext;
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verilog6502_wrapper u_dut(
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.clk(clk),
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.rst(rst),
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.s_apb(s_apb),
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.m_axil_rd(m_axil),
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.m_axil_wr(m_axil),
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.s_axi_rd(s_axi),
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.s_axi_wr(s_axi),
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.o_irq_ext(o_irq_ext),
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.i_irq_ext(i_irq_ext),
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.i_nmi_ext(i_nmi_ext)
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);
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endmodule |