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50f8791588f18f879ed7788d6974aced083d9a0f
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Byron Lathi 50f8791588 initial commit
2026-04-14 21:34:37 -07:00
fpga
initial commit
2026-04-14 21:34:37 -07:00
sim
initial commit
2026-04-14 21:34:37 -07:00
src
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sub
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.gitignore
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2026-04-14 21:34:37 -07:00
.gitmodules
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2026-04-14 21:34:37 -07:00
init_env.sh
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2026-04-14 21:34:37 -07:00
requirements.txt
initial commit
2026-04-14 21:34:37 -07:00
Description
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2.4 MiB
Languages
Verilog 79.7%
Tcl 14.5%
SystemVerilog 5.7%