242 lines
6.9 KiB
Verilog
242 lines
6.9 KiB
Verilog
/////////////////////////////////////////////////////////////////////////////
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// _____
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// / _______ Copyright (C) 2013-2020 Efinix Inc. All rights reserved.
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// / / \
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// / / .. /
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// / / .' /
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// __/ /.' /
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// __ \ /
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// /_/ /\ \_____/ /
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// ____/ \_______/
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//
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// *******************************
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// Revisions:
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// 1.0 Initial rev
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//
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// *******************************
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`timescale 1 ns / 1 ns
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module mac_pat_gen
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(
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//Globle Signals
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input clk,
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input rstn,
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//Control Interface
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input pat_gen_en,
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input [15:0] pat_gen_num,//When value is 0, it's infinite mode
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input [15:0] pat_gen_ipg,
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//MAC Protocol Signals
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input [47:0] dst_mac,
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input [47:0] src_mac,
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input [15:0] mac_dlen,
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//AXI4-Stream Interface
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input rclk,
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input rrstn,
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input [7:0] rdata,
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input rvalid,
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input rlast,
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output reg [7:0] tdata,
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output reg tvalid,
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output reg tlast,
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input tready
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);
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// Parameter Define
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localparam IDLE = 2'h0;
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localparam PAT_IPG = 2'h1;
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localparam PAT_GEN = 2'h2;
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// Register Define
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reg pat_gen_en_dl1;
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reg pat_gen_en_dl2;
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reg [1:0] cur_state;
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reg [1:0] next_state;
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reg pat_en;
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reg infinite_en;
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reg [15:0] num_cnt;
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reg [15:0] ipg_cnt;
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reg [15:0] pat_cnt;
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reg [15:0] pat_gen_num_r;
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reg [15:0] pat_gen_ipg_r;
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reg [47:0] dst_mac_r;
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reg [47:0] src_mac_r;
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reg [15:0] mac_dlen_r;
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// Wire Define
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/*----------------------------------------------------------------------------------*\
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The main code
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\*----------------------------------------------------------------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0) begin
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pat_gen_num_r <= 16'h0;
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pat_gen_ipg_r <= 16'h0;
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dst_mac_r <= 48'h0;
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src_mac_r <= 48'h0;
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mac_dlen_r <= 16'h0;
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end
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else begin
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pat_gen_num_r <= pat_gen_num;
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pat_gen_ipg_r <= pat_gen_ipg;
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dst_mac_r <= dst_mac;
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src_mac_r <= src_mac;
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mac_dlen_r <= mac_dlen;
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end
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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begin
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pat_gen_en_dl1 <= 1'h0;
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pat_gen_en_dl2 <= 1'h0;
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end
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else
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begin
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pat_gen_en_dl1 <= pat_gen_en;
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pat_gen_en_dl2 <= pat_gen_en_dl1;
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end
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end
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/*----------------------- FSM Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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cur_state <= IDLE;
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else
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cur_state <= next_state;
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end
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always @(*)
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begin
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case(cur_state)
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IDLE :
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if(pat_en == 1'b1)
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next_state = PAT_GEN;
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else
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next_state = IDLE;
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PAT_IPG :
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if((pat_en == 1'b1) || ((ipg_cnt == pat_gen_ipg_r) && (infinite_en == 1'b0) && (num_cnt == 16'h0)))
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next_state = IDLE;
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else if(ipg_cnt == pat_gen_ipg_r)
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next_state = PAT_GEN;
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else
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next_state = PAT_IPG;
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PAT_GEN :
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if((tlast == 1'b1) && (tready == 1'b1))
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next_state = PAT_IPG;
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else
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next_state = PAT_GEN;
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default :
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next_state = IDLE;
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endcase
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end
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/*----------------------- Generator Control Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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pat_en <= 1'h0;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
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pat_en <= 1'h1;
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else if((cur_state == IDLE) && (pat_en == 1'b1))
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pat_en <= 1'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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infinite_en <= 1'h0;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1) && (pat_gen_num_r == 16'h0))
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infinite_en <= 1'h1;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
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infinite_en <= 1'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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num_cnt <= 16'h0;
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else if((pat_gen_en_dl2 == 1'b0) && (pat_gen_en_dl1 == 1'b1))
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num_cnt <= pat_gen_num_r;
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else if((cur_state == PAT_GEN) && (tlast == 1'b1) && (tready == 1'b1) && (num_cnt != 16'h0))
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num_cnt <= num_cnt - 1'b1;
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end
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/*----------------------- Pattern Counter Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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ipg_cnt <= 16'h0;
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else if(cur_state == PAT_IPG)
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ipg_cnt <= ipg_cnt + 1'b1;
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else
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ipg_cnt <= 8'h0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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pat_cnt <= 16'h0;
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else if(cur_state != PAT_GEN)
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pat_cnt <= 16'h0;
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else if(tready == 1'b1)
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pat_cnt <= pat_cnt + 1'b1;
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end
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/*----------------------- Pattern Generator Region ----------------------------*/
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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tvalid <= 1'b0;
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else if((cur_state == PAT_GEN) && (pat_cnt == 16'h0) && (tready == 1'b1))
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tvalid <= 1'b1;
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else if((tready == 1'b1) && (tlast == 1'b1))
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tvalid <= 1'b0;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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tdata <= 8'h0;
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else if((cur_state == PAT_GEN) && (tready == 1'b1) && (pat_cnt <= 16'd14))
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case(pat_cnt[3:0])
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4'd0 : tdata <= dst_mac_r[5*8 +: 8];
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4'd1 : tdata <= dst_mac_r[4*8 +: 8];
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4'd2 : tdata <= dst_mac_r[3*8 +: 8];
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4'd3 : tdata <= dst_mac_r[2*8 +: 8];
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4'd4 : tdata <= dst_mac_r[1*8 +: 8];
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4'd5 : tdata <= dst_mac_r[0*8 +: 8];
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4'd6 : tdata <= src_mac_r[5*8 +: 8];
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4'd7 : tdata <= src_mac_r[4*8 +: 8];
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4'd8 : tdata <= src_mac_r[3*8 +: 8];
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4'd9 : tdata <= src_mac_r[2*8 +: 8];
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4'd10 : tdata <= src_mac_r[1*8 +: 8];
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4'd11 : tdata <= src_mac_r[0*8 +: 8];
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4'd12 : tdata <= mac_dlen_r[15:8];
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4'd13 : tdata <= mac_dlen_r[7:0];
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4'd14 : tdata <= 8'h0;//MAC First Data
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default : tdata <= tdata + 1'b1;
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endcase
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else if((cur_state == PAT_GEN) && (tready == 1'b1))
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tdata <= tdata + 1'b1;
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end
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always @(posedge clk or negedge rstn)
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begin
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if(rstn == 1'b0)
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tlast <= 1'b0;
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else if((tready == 1'b1) && (cur_state == PAT_GEN) && (pat_cnt == mac_dlen_r+16'd13))
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tlast <= 1'b1;
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else if(tready == 1'b1)
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tlast <= 1'b0;
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end
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endmodule
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