230 lines
10 KiB
VHDL
230 lines
10 KiB
VHDL
--------------------------------------------------------------------------------
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-- Copyright (C) 2013-2025 Efinix Inc. All rights reserved.
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--
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-- This document contains proprietary information which is
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-- protected by copyright. All rights are reserved. This notice
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-- refers to original work by Efinix, Inc. which may be derivitive
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-- of other work distributed under license of the authors. In the
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-- case of derivative work, nothing in this notice overrides the
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-- original author's license agreement. Where applicable, the
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-- original license agreement is included in it's original
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-- unmodified form immediately below this header.
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--
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-- WARRANTY DISCLAIMER.
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-- THE DESIGN, CODE, OR INFORMATION ARE PROVIDED “AS IS” AND
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-- EFINIX MAKES NO WARRANTIES, EXPRESS OR IMPLIED WITH
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-- RESPECT THERETO, AND EXPRESSLY DISCLAIMS ANY IMPLIED WARRANTIES,
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-- INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR
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-- PURPOSE. SOME STATES DO NOT ALLOW EXCLUSIONS OF AN IMPLIED
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-- WARRANTY, SO THIS DISCLAIMER MAY NOT APPLY TO LICENSEE.
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--
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-- LIMITATION OF LIABILITY.
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-- NOTWITHSTANDING ANYTHING TO THE CONTRARY, EXCEPT FOR BODILY
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-- INJURY, EFINIX SHALL NOT BE LIABLE WITH RESPECT TO ANY SUBJECT
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-- MATTER OF THIS AGREEMENT UNDER TORT, CONTRACT, STRICT LIABILITY
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-- OR ANY OTHER LEGAL OR EQUITABLE THEORY (I) FOR ANY INDIRECT,
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-- SPECIAL, INCIDENTAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES OF ANY
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-- CHARACTER INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF
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-- GOODWILL, DATA OR PROFIT, WORK STOPPAGE, OR COMPUTER FAILURE OR
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-- MALFUNCTION, OR IN ANY EVENT (II) FOR ANY AMOUNT IN EXCESS, IN
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-- THE AGGREGATE, OF THE FEE PAID BY LICENSEE TO EFINIX HEREUNDER
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-- (OR, IF THE FEE HAS BEEN WAIVED, $100), EVEN IF EFINIX SHALL HAVE
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-- BEEN INFORMED OF THE POSSIBILITY OF SUCH DAMAGES. SOME STATES DO
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-- NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR
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-- CONSEQUENTIAL DAMAGES, SO THIS LIMITATION AND EXCLUSION MAY NOT
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-- APPLY TO LICENSEE.
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--
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--------------------------------------------------------------------------------
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------------- Begin Cut here for COMPONENT Declaration ------
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component gAXIM_2to1_switch is
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port (
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rst_n : in std_logic;
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clk : in std_logic;
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s_axi_awvalid : in std_logic_vector(1 downto 0);
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s_axi_awaddr : in std_logic_vector(63 downto 0);
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s_axi_awlock : in std_logic_vector(3 downto 0);
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s_axi_awready : out std_logic_vector(1 downto 0);
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s_axi_arvalid : in std_logic_vector(1 downto 0);
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s_axi_araddr : in std_logic_vector(63 downto 0);
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s_axi_arlock : in std_logic_vector(3 downto 0);
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s_axi_arready : out std_logic_vector(1 downto 0);
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s_axi_wvalid : in std_logic_vector(1 downto 0);
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s_axi_wlast : in std_logic_vector(1 downto 0);
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s_axi_wid : in std_logic_vector(15 downto 0);
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s_axi_bready : in std_logic_vector(1 downto 0);
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s_axi_bresp : out std_logic_vector(3 downto 0);
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s_axi_rready : in std_logic_vector(1 downto 0);
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s_axi_bid : out std_logic_vector(15 downto 0);
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s_axi_rid : out std_logic_vector(15 downto 0);
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s_axi_wdata : in std_logic_vector(255 downto 0);
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s_axi_rdata : out std_logic_vector(255 downto 0);
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s_axi_rresp : out std_logic_vector(3 downto 0);
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s_axi_bvalid : out std_logic_vector(1 downto 0);
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s_axi_rvalid : out std_logic_vector(1 downto 0);
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s_axi_rlast : out std_logic_vector(1 downto 0);
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s_axi_wstrb : in std_logic_vector(31 downto 0);
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m_axi_awvalid : out std_logic_vector(0 to 0);
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m_axi_awaddr : out std_logic_vector(31 downto 0);
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m_axi_awlock : out std_logic_vector(1 downto 0);
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m_axi_awready : in std_logic_vector(0 to 0);
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m_axi_arvalid : out std_logic_vector(0 to 0);
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m_axi_araddr : out std_logic_vector(31 downto 0);
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m_axi_arlock : out std_logic_vector(1 downto 0);
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m_axi_arready : in std_logic_vector(0 to 0);
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m_axi_wvalid : out std_logic_vector(0 to 0);
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m_axi_wlast : out std_logic_vector(0 to 0);
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m_axi_bready : out std_logic_vector(0 to 0);
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m_axi_bresp : in std_logic_vector(1 downto 0);
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m_axi_rready : out std_logic_vector(0 to 0);
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m_axi_bid : in std_logic_vector(7 downto 0);
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m_axi_rid : in std_logic_vector(7 downto 0);
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m_axi_wdata : out std_logic_vector(127 downto 0);
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m_axi_rdata : in std_logic_vector(127 downto 0);
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m_axi_rresp : in std_logic_vector(1 downto 0);
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m_axi_bvalid : in std_logic_vector(0 to 0);
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m_axi_rvalid : in std_logic_vector(0 to 0);
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m_axi_rlast : in std_logic_vector(0 to 0);
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m_axi_wstrb : out std_logic_vector(15 downto 0);
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m_axi_wready : in std_logic_vector(0 to 0);
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s_axi_wready : out std_logic_vector(1 downto 0);
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s_axi_awprot : in std_logic_vector(7 downto 0);
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s_axi_awcache : in std_logic_vector(7 downto 0);
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s_axi_awqos : in std_logic_vector(7 downto 0);
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s_axi_awuser : in std_logic_vector(5 downto 0);
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s_axi_arqos : in std_logic_vector(7 downto 0);
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s_axi_arcache : in std_logic_vector(7 downto 0);
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m_axi_awprot : out std_logic_vector(3 downto 0);
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s_axi_arid : in std_logic_vector(15 downto 0);
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s_axi_arsize : in std_logic_vector(5 downto 0);
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s_axi_arlen : in std_logic_vector(15 downto 0);
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s_axi_arburst : in std_logic_vector(3 downto 0);
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s_axi_arprot : in std_logic_vector(7 downto 0);
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s_axi_awid : in std_logic_vector(15 downto 0);
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s_axi_awburst : in std_logic_vector(3 downto 0);
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s_axi_awlen : in std_logic_vector(15 downto 0);
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s_axi_awsize : in std_logic_vector(5 downto 0);
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m_axi_awid : out std_logic_vector(7 downto 0);
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m_axi_awburst : out std_logic_vector(1 downto 0);
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m_axi_awlen : out std_logic_vector(7 downto 0);
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m_axi_awsize : out std_logic_vector(2 downto 0);
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m_axi_awcache : out std_logic_vector(3 downto 0);
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m_axi_awqos : out std_logic_vector(3 downto 0);
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m_axi_awuser : out std_logic_vector(2 downto 0);
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m_axi_arprot : out std_logic_vector(3 downto 0);
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m_axi_arburst : out std_logic_vector(1 downto 0);
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m_axi_arlen : out std_logic_vector(7 downto 0);
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m_axi_arsize : out std_logic_vector(2 downto 0);
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m_axi_arcache : out std_logic_vector(3 downto 0);
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m_axi_arqos : out std_logic_vector(3 downto 0);
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m_axi_aruser : out std_logic_vector(2 downto 0);
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m_axi_awregion : out std_logic_vector(3 downto 0);
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m_axi_arregion : out std_logic_vector(3 downto 0);
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m_axi_arid : out std_logic_vector(7 downto 0);
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m_axi_wuser : out std_logic_vector(2 downto 0);
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m_axi_ruser : in std_logic_vector(2 downto 0);
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m_axi_buser : in std_logic_vector(2 downto 0);
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s_axi_aruser : in std_logic_vector(5 downto 0);
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s_axi_wuser : in std_logic_vector(5 downto 0);
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s_axi_buser : out std_logic_vector(5 downto 0);
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s_axi_ruser : out std_logic_vector(5 downto 0)
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);
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end component gAXIM_2to1_switch;
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---------------------- End COMPONENT Declaration ------------
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------------- Begin Cut here for INSTANTIATION Template -----
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u_gAXIM_2to1_switch : gAXIM_2to1_switch
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port map (
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rst_n => rst_n,
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clk => clk,
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s_axi_awvalid => s_axi_awvalid,
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s_axi_awaddr => s_axi_awaddr,
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s_axi_awlock => s_axi_awlock,
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s_axi_awready => s_axi_awready,
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s_axi_arvalid => s_axi_arvalid,
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s_axi_araddr => s_axi_araddr,
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s_axi_arlock => s_axi_arlock,
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s_axi_arready => s_axi_arready,
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s_axi_wvalid => s_axi_wvalid,
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s_axi_wlast => s_axi_wlast,
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s_axi_wid => s_axi_wid,
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s_axi_bready => s_axi_bready,
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s_axi_bresp => s_axi_bresp,
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s_axi_rready => s_axi_rready,
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s_axi_bid => s_axi_bid,
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s_axi_rid => s_axi_rid,
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s_axi_wdata => s_axi_wdata,
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s_axi_rdata => s_axi_rdata,
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s_axi_rresp => s_axi_rresp,
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s_axi_bvalid => s_axi_bvalid,
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s_axi_rvalid => s_axi_rvalid,
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s_axi_rlast => s_axi_rlast,
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s_axi_wstrb => s_axi_wstrb,
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m_axi_awvalid => m_axi_awvalid,
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m_axi_awaddr => m_axi_awaddr,
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m_axi_awlock => m_axi_awlock,
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m_axi_awready => m_axi_awready,
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m_axi_arvalid => m_axi_arvalid,
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m_axi_araddr => m_axi_araddr,
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m_axi_arlock => m_axi_arlock,
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m_axi_arready => m_axi_arready,
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m_axi_wvalid => m_axi_wvalid,
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m_axi_wlast => m_axi_wlast,
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m_axi_bready => m_axi_bready,
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m_axi_bresp => m_axi_bresp,
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m_axi_rready => m_axi_rready,
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m_axi_bid => m_axi_bid,
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m_axi_rid => m_axi_rid,
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m_axi_wdata => m_axi_wdata,
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m_axi_rdata => m_axi_rdata,
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m_axi_rresp => m_axi_rresp,
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m_axi_bvalid => m_axi_bvalid,
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m_axi_rvalid => m_axi_rvalid,
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m_axi_rlast => m_axi_rlast,
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m_axi_wstrb => m_axi_wstrb,
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m_axi_wready => m_axi_wready,
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s_axi_wready => s_axi_wready,
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s_axi_awprot => s_axi_awprot,
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s_axi_awcache => s_axi_awcache,
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s_axi_awqos => s_axi_awqos,
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s_axi_awuser => s_axi_awuser,
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s_axi_arqos => s_axi_arqos,
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s_axi_arcache => s_axi_arcache,
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m_axi_awprot => m_axi_awprot,
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s_axi_arid => s_axi_arid,
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s_axi_arsize => s_axi_arsize,
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s_axi_arlen => s_axi_arlen,
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s_axi_arburst => s_axi_arburst,
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s_axi_arprot => s_axi_arprot,
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s_axi_awid => s_axi_awid,
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s_axi_awburst => s_axi_awburst,
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s_axi_awlen => s_axi_awlen,
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s_axi_awsize => s_axi_awsize,
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m_axi_awid => m_axi_awid,
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m_axi_awburst => m_axi_awburst,
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m_axi_awlen => m_axi_awlen,
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m_axi_awsize => m_axi_awsize,
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m_axi_awcache => m_axi_awcache,
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m_axi_awqos => m_axi_awqos,
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m_axi_awuser => m_axi_awuser,
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m_axi_arprot => m_axi_arprot,
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m_axi_arburst => m_axi_arburst,
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m_axi_arlen => m_axi_arlen,
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m_axi_arsize => m_axi_arsize,
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m_axi_arcache => m_axi_arcache,
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m_axi_arqos => m_axi_arqos,
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m_axi_aruser => m_axi_aruser,
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m_axi_awregion => m_axi_awregion,
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m_axi_arregion => m_axi_arregion,
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m_axi_arid => m_axi_arid,
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m_axi_wuser => m_axi_wuser,
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m_axi_ruser => m_axi_ruser,
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m_axi_buser => m_axi_buser,
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s_axi_aruser => s_axi_aruser,
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s_axi_wuser => s_axi_wuser,
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s_axi_buser => s_axi_buser,
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s_axi_ruser => s_axi_ruser
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);
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------------------------ End INSTANTIATION Template ---------
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