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ef6b5f066923a648096a5d73f56519c64b4bcdce
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Byron Lathi ef6b5f0669 Factor out verilog6502 into its own submodule
2026-04-18 18:55:40 -07:00
fpga
initial commit
2026-04-14 21:34:37 -07:00
sub
Factor out verilog6502 into its own submodule
2026-04-18 18:55:40 -07:00
.gitignore
initial commit
2026-04-14 21:34:37 -07:00
.gitmodules
Factor out verilog6502 into its own submodule
2026-04-18 18:55:40 -07:00
init_env.sh
initial commit
2026-04-14 21:34:37 -07:00
requirements.txt
initial commit
2026-04-14 21:34:37 -07:00
Description
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2.4 MiB
Languages
Verilog 79.7%
Tcl 14.5%
SystemVerilog 5.7%